29 results about "Test array" patented technology

The embodiment of the invention provides a transducer echo line sequence test method and a transducer echo line sequence test device, and the method comprises the steps: enabling a detection surface and a horizontal plane to form a first angle in an echo detection state, comparing waveform data of feedback signals obtained by reflecting the ultrasonic signals emitted by the plurality of test array elements through the detection surface with preset qualified data to determine a performance result of the transducer; in the line sequence detection state, a second angle is formed between the detection surface and the horizontal plane, and the actual flight time difference value of each adjacent test array element in the plurality of test array elements is determined according to waveform data of feedback signals obtained by reflecting ultrasonic signals emitted by the plurality of test array elements through the detection surface, and according to a comparison relation between a difference value between the actual flight time difference value and the theoretical flight time difference value and a preset threshold value, whether welding of each test array element is correct or not is determined. Therefore, an echo performance detection function and a multi-array element line sequence detection function can be integrated.

The present application relates to high-voltage insulation gas humidity detection technical field, especially to a kind of high-voltage electrical equipment gas humidity detection circuit, method, device and storage medium, the present application method first obtains multiple test arrays;Then the multiple test arrays are respectively substituted into standard capacitance equation, obtain the standard capacitance estimated value of humidity sensor;Then according to the standard capacitance estimated value determine the deviation of standard capacitance application value, and when deviation is greater than deviation threshold, again through the standard capacitance equation obtains standard capacitance estimated value;Finally, according to the return value of humidity sensor, gas temperature and according to the standard capacitance estimated value selected humidity curve equation determines gas humidity.The present application embodiment selects corresponding humidity curve equation by the standard capacitance value determined to complete humidity detection, reduces the problem of inaccurate data caused by sensor drift.

A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

The utility model relates to the field of circuit board testing, in particular to a universal test fixture for a circuit board. The device comprises a universal base electrically connected with test equipment, the universal base is provided with a conversion module and an output module, the conversion module is electrically connected with the output module, the output module is detachably and fixedly provided with a test head assembly, and the test head assembly is electrically connected with the output module; when the circuit boards of different models need to be tested, the test array points on the output module are switched through the conversion module, and then the circuit boards of different models can be tested only by replacing the corresponding test head assemblies without additionally arranging jigs, so that time and labor are saved, and the cost is saved.

The application discloses a low-leakage on-chip interconnection signal line system and an addressable test array circuit, and relates to the technical field of solving the problem of leakage of interconnection signal lines. The low-leakage on-chip interconnection signal line system comprises interconnection signal lines and signal protection channels which can be configured to have equal voltages, wherein the signal protection channels comprise: a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnection signal lines in the vertical projection direction of a chip, and the interconnection signal lines are located between the first shielding layer and the second shielding layer; a first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer respectively, and the interconnection signal lines are located between the first shielding wall and the second shielding wall.

The application provides a system, electronic equipment and storage medium for continuous testing of array devices, comprising a first host computer and a probe station; the first host computer sends a scanning path to the probe station to control the probe station to perform scanning test on a to-be-tested array device; a tray of the probe station moves according to path points set by the scanning path, reaches a specified position, then moves the tray upward to connect a probe and an electrode of the to-be-tested array device, and the to-be-tested array device is tested by an electronic testing device according to a test instruction sent by a second host computer, and the above process is repeated until all electrodes of the to-be-tested array device are tested. Scanning test of any test parameter can be realized on any array device, and then data visualization is performed in combination with a detection position coordinate and a test result of the position, thereby providing comprehensive and effective test data for array devices of different shapes.

The invention discloses a pharmacodynamic test method for a cough relieving mixture, which comprises the following steps: constructing four core pharmacodynamic test sub-models containing ammonia water to cause young mouse cough, citric acid to cause young guinea pig cough, rabbit in-vitro trachea cilia mucus movement and young mouse trachea phenol red excretion and a body model of a test result analysis sub-model; each pharmacodynamic test sub-model is provided with a plurality of groups of test arrays and test individuals; pathogen data is imported to generate a simulated disease scene, and a corresponding drug sequence is called to intervene and collect physiological index change data; and multi-dimensional pharmacodynamic parameters are evaluated through the analysis sub-model, and a dose-effect relation curve and an evaluation report are generated. According to the invention, a parallel verification system for antitussive and expectorant tests is formed, the antitussive effective dose, the expectorant effective dose and the effective dose range under the dual action of the medicine are determined through multi-model cross validation, the accuracy degree of judging the effectiveness of the medicine is greatly improved, and a reliable method support is provided for evaluating the efficacy of the cough-stopping mixture.

The invention relates to an electrical property test structure and a test method thereof, and relates to the technical field of integrated circuits, the structure comprises a test array which comprises a target transistor and a plurality of peripheral areas surrounding the target transistor and distributed along the radial direction of the test array, and the test array is configured to receive a test voltage according to the received test voltage; outputting the to-be-measured current generated by the target transistor and / or the plurality of peripheral regions; the gating device is connected with the target transistor and the plurality of peripheral areas and is configured to respond to a received gating signal, and at least one peripheral area is connected with the target transistor; and / or connecting the plurality of peripheral regions to adjust the current to be tested generated by the test array; wherein the test array comprises to-be-tested current of the peripheral area, and the to-be-tested current is in proportional relation with to-be-tested current only comprising the target transistor. The structure and the method are completely compatible with the existing processing technology, and are suitable for platforms with different technical nodes. The new structure designed by the method can eliminate the influence of test noise, and more accurate MOS electric leakage can be obtained.

This disclosure provides a semiconductor test structure and its manufacturing method, relating to the field of semiconductor technology. The semiconductor test structure includes: a test array region, comprising a first array of active test regions arranged in an array, the angle between the extension direction of the first active test regions and a first direction being a preset angle, wherein two adjacent second active test regions located in different columns are connected to each other at a first boundary of the test array region along a second direction; and a plurality of test conductive line groups arranged along the first direction, wherein each test conductive line group includes two adjacent test conductive lines, each test conductive line extending along the second direction through the test array region, and the test conductive lines in the plurality of test conductive line groups are correspondingly coupled to the first active test regions, wherein the first ends of the two adjacent test conductive lines in each test conductive line group are electrically connected through interconnected second active test regions. This disclosure can improve the reliability and stability of test bit lines.

The invention discloses a transistor variability test characterization method, device and equipment, relates to the technical field of semiconductor characterization and test, and is used for fitting the variability of a device in high sigma distribution. Comprising the following steps: determining a plurality of to-be-tested devices in a test array; applying electric stress to the plurality of to-be-tested devices in the test array and testing to obtain test experiment data; on the basis of test experiment data, statistical distribution of device parameters changing along with time is constructed; and fitting the statistical distribution by using the statistical model to obtain a fitting model so as to complete time domain variability test analysis and model fitting. According to the technical scheme provided by the invention, the reliability and variability of a large number of semiconductor devices can be efficiently tested in batches, the test efficiency and the data statistics significance are remarkably improved, and the statistical distribution of device parameters drifting along with time is accurately described; the finally obtained fitting model can predict the variability and reliability of the semiconductor device more accurately.

Embodiments disclosed herein provide cooling for a test array (e.g., a semiconductor test array) using a 2-phase refrigerant. Testing can be performed without any added insulation, which improves test site density significantly. The refrigerant can be provided by any suitable refrigerant source, such as a pump or valve-controlled pressure chamber, for example, and can be provided to a cold plate of a test site, for example. The cold plate can include a flow field or flow channels for guiding the refrigerant to evenly cool surfaces and / or prevent condensation forming on outer surfaces of the cold plate or test site.

The disclosure provides a visual evoked working memory evaluation system and method, which can be applied to the fields of neuroscience technology and computer vision technology. The system comprises: a control device configured to execute multiple rounds of display tasks, wherein the (i-1)th round of display tasks is controlled to display a memory array image, a gray scale stimulus image and a test array image based on the (i-1)th task intensity parameter and the (i-1)th stimulus intensity parameter; an interaction device configured to determine the (i-1)th feedback result in response to the (i-1)th feedback operation of a target object during the execution of the (i-1)th round of display tasks; and an evaluation device configured to determine the (i-1)th working memory capacity evaluation result based on the (i-1)th feedback result, and determine the (i)th task intensity parameter and the (i)th stimulus intensity parameter based on the (i-1)th feedback result and the (i-1)th working memory capacity evaluation result to obtain the (i)th round of display tasks.

The application provides a semiconductor electrical property measurement structure, which comprises a test array, the test array comprises a plurality of test units, and the plurality of test units are arranged in a matrix, wherein the test unit comprises at least two transistors, and the plurality of transistors are electrically connected in sequence, adjacent transistors in the test unit share the same electrode; in the test array, the middle electrode of part of the test units is grounded, and the edge electrode serves as a first signal output end; the middle electrode of another part of the test units serves as a second signal output end, and the edge electrode is grounded; when the electrode of the transistor is in a high resistance state, the output current of the test unit is reduced, and the range of the reduction of the output current represents the type of the electrode in the high resistance state in the test unit. The application can monitor the distribution behavior of a small number of defective vias existing in a large number of dense vias, and locate the position of the defective via.

This invention provides a chip programming and testing array device, including a workbench. A support platform is provided on the surface of the workbench, and a support frame is fixedly connected to the surface of the workbench. An electric push rod is fixedly connected to the surface of the support frame, and a mounting plate is fixedly connected to the output end of the electric push rod. In this invention, the spring force firmly secures the first and second clips into the slot, thereby fixing the probe board. When the probe body needs to be replaced according to usage requirements, the first and second pressure plates on both sides of the clip block are pressed, causing the first and second clips to slide inside the clip block. The clip block is then removed from the mounting plate, making the probe board replacement operation simple and quick, eliminating the need for complex tools and lengthy debugging, significantly reducing the time spent replacing the probe board, and improving the conversion efficiency of the device for programming and testing different chips.

The invention provides a semiconductor electrical property measurement structure, which comprises a test array, the test array comprises a plurality of test units, the plurality of test units are distributed in a matrix, each test unit comprises at least two transistors, the plurality of transistors are electrically connected in sequence, and in the test units, adjacent transistors share the same electrode; in the test array, the middle electrodes of part of the test units are grounded, the edge electrodes serve as first signal output ends, the middle electrodes of the other part of the test units serve as second signal output ends, and the edge electrodes are grounded; when the electrode of the transistor is in a high-resistance state, the output current of the test unit is reduced, and the decreasing amplitude range of the output current represents the type of the electrode in the high-resistance state in the test unit. According to the invention, the distribution behavior of a small number of defective via holes in a large number of dense via holes can be monitored, and the positions of the defective via holes can be positioned.

The invention relates to an addressable test circuit and method for the reliability of a subsequent process, and the circuit comprises an addressing circuit which is used for receiving a binary address signal, decoding the binary address signal, and generating a plurality of gating signals; a switching circuit connected with the addressing circuit and configured to selectively transmit an input test signal to a corresponding output line in response to the gating signal; the to-be-tested array comprises a plurality of to-be-tested units, and each to-be-tested unit is connected to one output line of the switching circuit so as to receive the input test signal; the unit to be tested comprises a metal interconnection layer; in the testing process, the failure mode or the design parameter critical value of the metal interconnection structure is judged through the input testing signal and the output signal obtained from the unit to be tested. According to the method, the process optimization efficiency can be improved, the failure can be directly positioned to the specific level and structure, large-scale DOE trial and error are reduced, and the research and development iteration and yield climbing period is shortened.

The utility model relates to the technical field of camera module testing, in particular to a test graphic card, which is used for testing an array camera module and comprises a rectangular test surface which comprises a transverse datum line, a longitudinal datum line and a plurality of test units distributed in an array mode. The test unit is rectangular and is internally provided with a feature mark; the diagonal line of the test unit is a full field of view which can be shot by a single camera module, and the test unit is provided with four feature marks on each of the 0.5 field of view and the 0.92 field of view; wherein along the direction of the transverse reference line, partial feature marks of the adjacent test units on the 0.92 field of view coincide; in the direction of the longitudinal reference line, part of the feature marks of the adjacent test units in the 0.5 view field and the 0.92 view field coincide, so that the aliasing phenomenon of the feature marks on the adjacent test units is avoided, and the definition difference of the image edges of the test units shot by a single camera module is further avoided; further, the image direction is caused to the splicing and the array camera module cannot be tested.

The invention provides a gradient magnetic field testing method and device for a magnetic shielding barrel. The gradient magnetic field testing device comprises a magnetic gradient testing unit, a supporting assembly and a connecting rod. An atom magnetometer can be nested in the magnetic gradient test unit to form a single magnetic field test unit. A plurality of magnetic gradient test units can be combined through the connecting rods to form a magnetic field gradient test array to adapt to the space in the shielding barrel. The magnetic field gradient test array can be connected with the supporting assembly, so that the magnetic field gradient test array is fixed in the shielding barrel and has mobility, and magnetic field distribution in the shielding barrel can be completely tested. According to the technical scheme, the technical problems that in the prior art, a visual large-range magnetic field imaging device is lacked, actual magnetic field gradient testing and compensation are lacked for a magnetic shielding barrel which is actually produced, processed and manufactured, and the space gradient in the magnetic shielding barrel can serve as an error term to be introduced into a magnetometer testing result are solved.

The utility model discloses a current test probe, can directly set up the one end of voltage needle with thorn with the measured object contact in the test, and the thorn is used for breaking the oxide film, makes the probe head and the battery pole post contact well. The elastic sheet has the elastic force of making the first fixed block and the second fixed block away, so that the probe head and the measured object contact, the probe head is connected with the test platform, and the test platform can show the current data and voltage data of the measured object. The elastic sheet has high reliability, is not easy to fatigue failure, can ensure the close contact between the probe head and the measured object, improves the measurement precision and data consistency, guarantees the long -term stable electrical connection, especially suitable for the test occasion of long -time continuous work, the elastic sheet is relatively short to spring length, reduces the overall size, is favorable to the construction denser test array, improves production efficiency, the elastic sheet is relatively simple to spring installation, simplifies the assembly process, when the elastic sheet is tired, is easy to replace, and the maintenance cost is reduced.

The invention provides a modularized multifunctional contact pressure anchoring test device and method, and the device is characterized in that a first positioning part on a positioning registration module is matched with a first positioning hole in a non-packaging sensor, and is matched with a second positioning hole in a signal switching system module; aligning each layer structure of the non-packaged sensor and the signal switching system module up and down, and aligning a contact of the signal switching system module with a test point of the non-packaged sensor; a second positioning piece on the positioning registration module is matched with a third positioning hole in the pressurization module and is matched with a fourth positioning hole in the non-packaged sensor, so that a pressurization array of the pressurization module is aligned with a test array of the non-packaged sensor; the signal transfer system module is connected with the non-packaged sensor and is connected with the multi-channel LCR tester; and the pressurizing module is used for pressurizing a test point of the non-packaged sensor. According to the invention, an accurate, efficient and repeatable pressure-capacitance signal anchoring test is provided for a non-packaged micro flexible pressure sensor array.

This invention provides a non-volatile memory and its automatic repair method, comprising: a main array for storing data and ECC check data; a test array; a read circuit for performing a read operation on the test array for each read operation on the main array; a refresh initiation circuit for counting the number of flipped bits in the test array based on the data read from the test array each time, determining whether the number of flipped bits is greater than or equal to a preset threshold, and if so, initiating a refresh operation on both the test array and the main array; and a write circuit for executing the refresh operation on both the test array and the main array. This invention can mitigate the impact of read interference rate.

The utility model relates to a device for testing the performance of an array type single-photon detector, which aims to solve the technical problem that the existing means for testing the performance of the array type single-photon detector is not mature yet, and adopts the technical scheme that the device comprises an adjustable light source module, a beam expanding module, a testing module and a data analyzing and processing module, the adjustable laser emitter emits laser, the laser is reflected and attenuated by the three reflectors and the two attenuators and then enters the beam expanding module, the beam expanding module comprises two plano-convex lenses and an adjustable lens sleeve and is located on a reflected light path, and the testing module is a micro-lens array located on the light path. The array type single-photon detector and the optical fiber power meter are respectively connected with the array type single-photon detector and the optical fiber power meter; and a time-dependent single-photon counter in the data analysis processing module is electrically connected with the array single-photon detector and the computer respectively. According to the utility model, through testing the detection efficiency, the detection efficiency consistency, the dark count, the saturation count rate, the dead time, the time jitter and the overall time jitter of the array type single-photon detector, the performance of the array type single-photon detector is comprehensively represented.

The invention discloses a parallel test system and method for high and low temperature performance test of fuze circuit jointed boards, and the system comprises a modular test array which is provided with a plurality of test units and is used for collecting the function signals of a plurality of tested fuze circuit jointed boards in parallel, comprising an ignition signal, a charging signal, a power-on signal, fuze operation records and test environment information; the communication transfer module is used for transmitting a test instruction issued after the test control host executes the test program to the modular test array and transmitting test data of the modular test array to the test control host; and the test control host is used for displaying the test state of the modular test array, setting a test standard value, adjusting the test temperature, comparing test data with the test standard value to obtain a processing test result and giving corresponding error information of the tested fuze circuit jointed board. The test method based on the system can realize parallel automatic detection of the fuze circuit jointed board.

The application relates to the technical field of electronic module testing, and discloses a serial testing method and system integrating multiple controllers and a storage medium. The method first extracts three types of independent testing modules, namely, a power supply testing module, a first communication testing module and a second communication testing module, from a testing device list, then establishes a time-sharing serial testing array comprising three time-sharing units, each time-sharing unit is provided with a time-sharing selection switch matrix, a plurality of controllers to be tested can be connected at the same time, and the three types of independent testing modules are respectively connected. Then, according to a time-sharing testing sequence instruction, each time-sharing unit is started and stopped in turn, the corresponding switches are turned on for testing, and the switches are turned off for non-testing, each time-sharing unit does not work at the same time, a first time length is set for waiting after power supply testing, a second time length is set for waiting after first communication testing, and the second time length is shorter than the first time length. The method realizes efficient utilization of testing module resources, improves the serial testing efficiency of multiple controllers, and guarantees the stability of the testing process and the accuracy of the testing result.

This invention provides a semiconductor process testing device, comprising: a substrate having a MOS device; wherein the gate of the MOS device is electrically connected to a first test node, the source of the MOS device is electrically connected to a second test node, and the body of the MOS device is electrically connected to a third test node; a bottom metal layer disposed on the substrate and electrically connected to the drain of the MOS device; a process test array disposed above the bottom metal layer; and a test interconnect structure disposed above the bottom metal layer, spaced apart from the process test array, electrically connected to the bottom metal layer, and electrically connected to a fourth test node. This invention can test the damage to the MOS device caused by the PID effect during the semiconductor device fabrication process, which helps in the optimization of semiconductor device processes and improves the performance of semiconductor devices.

The invention provides a semiconductor test structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor test structure comprises a test array area which comprises first test active areas arranged in an array mode, the included angle range between the extending direction of the first test active areas and the first direction is a preset angle, and the first boundary of the test array area in the second direction is provided with a first test area and a second test area. The two second test active areas which are located in different columns and are adjacent in position are connected with each other; the plurality of test conductor wire groups are arranged along the first direction, each test conductor wire group comprises two test conductor wires which are adjacently arranged, each test conductor wire extends and penetrates through the test array area along the second direction, the test conductor wires in the plurality of test conductor wire groups are correspondingly coupled with the first test active area, and the test conductor wires in the plurality of test conductor wire groups are correspondingly coupled with the second test active area. And the first ends of the two adjacent test conductive wires in each test conductive wire group are electrically connected through the second test active areas which are connected with each other. The reliability and the stability of the test bit line can be improved.

The invention discloses a test structure and a test method of the test structure, and the test structure comprises at least two test array units, each test array unit is provided with a different number of transistors; grid electrodes and source electrodes of the transistors in all the test array units are electrically connected with the substrate; the drain electrodes of the transistors in each test array unit are electrically connected. A plurality of test array units are arranged, and grid electrodes and source electrodes of transistors in all the test array units are electrically connected with a substrate, so that when different test array units are measured, the introduced leakage current values of other paths are close, and in the subsequent calculation process, the introduced leakage current values of other paths can be counteracted mutually; therefore, the calculation precision of the leakage current of the single transistor is improved. In addition, due to the arrangement of more test array units, the influence caused by abnormal leakage current of part of the test array units can be eliminated, so that the calculation precision of the leakage current of a single transistor is improved.

Systems and methods for a digital pixel circuit for liquid crystal displays are provided. The design includes a dual-voltage pixel design, a two-transistor level-shift circuit design, self-adjusting transistor bias circuitry; and an optional on-chip test-array to determine die-specific design-center values for critical transistor leakage and threshold parameters. Level shift design simplicity, small pixel pitch, and applicability for small display applications such as microdisplays, are among the various benefits and advantages obtained.

The application relates to an electrical test structure and a test method thereof, and relates to the technical field of integrated circuits. The structure comprises a test array, a target transistor, and a plurality of peripheral regions surrounding the target transistor and distributed radially along the test array. The structure is configured to output a test current generated by the target transistor and / or the plurality of peripheral regions according to a received test voltage. A gate is connected to the target transistor and the plurality of peripheral regions. The gate is configured to connect at least one peripheral region to the target transistor in response to a received gate signal, and / or connect the plurality of peripheral regions to adjust the test current generated by the test array. The test current of the peripheral regions is in proportional relationship with the test current of the target transistor. The structure and the method are fully compatible with existing process technology and are suitable for platforms of different technology nodes. The new structure designed by the method can eliminate the influence of test noise and obtain more accurate MOS leakage.