14 results about "Test array" patented technology

A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

The application discloses a low-leakage on-chip interconnection signal line system and an addressable test array circuit, and relates to the technical field of solving the problem of leakage of interconnection signal lines. The low-leakage on-chip interconnection signal line system comprises interconnection signal lines and signal protection channels which can be configured to have equal voltages, wherein the signal protection channels comprise: a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnection signal lines in the vertical projection direction of a chip, and the interconnection signal lines are located between the first shielding layer and the second shielding layer; a first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer respectively, and the interconnection signal lines are located between the first shielding wall and the second shielding wall.

The invention discloses a pharmacodynamic test method for a cough relieving mixture, which comprises the following steps: constructing four core pharmacodynamic test sub-models containing ammonia water to cause young mouse cough, citric acid to cause young guinea pig cough, rabbit in-vitro trachea cilia mucus movement and young mouse trachea phenol red excretion and a body model of a test result analysis sub-model; each pharmacodynamic test sub-model is provided with a plurality of groups of test arrays and test individuals; pathogen data is imported to generate a simulated disease scene, and a corresponding drug sequence is called to intervene and collect physiological index change data; and multi-dimensional pharmacodynamic parameters are evaluated through the analysis sub-model, and a dose-effect relation curve and an evaluation report are generated. According to the invention, a parallel verification system for antitussive and expectorant tests is formed, the antitussive effective dose, the expectorant effective dose and the effective dose range under the dual action of the medicine are determined through multi-model cross validation, the accuracy degree of judging the effectiveness of the medicine is greatly improved, and a reliable method support is provided for evaluating the efficacy of the cough-stopping mixture.

The invention relates to an electrical property test structure and a test method thereof, and relates to the technical field of integrated circuits, the structure comprises a test array which comprises a target transistor and a plurality of peripheral areas surrounding the target transistor and distributed along the radial direction of the test array, and the test array is configured to receive a test voltage according to the received test voltage; outputting the to-be-measured current generated by the target transistor and / or the plurality of peripheral regions; the gating device is connected with the target transistor and the plurality of peripheral areas and is configured to respond to a received gating signal, and at least one peripheral area is connected with the target transistor; and / or connecting the plurality of peripheral regions to adjust the current to be tested generated by the test array; wherein the test array comprises to-be-tested current of the peripheral area, and the to-be-tested current is in proportional relation with to-be-tested current only comprising the target transistor. The structure and the method are completely compatible with the existing processing technology, and are suitable for platforms with different technical nodes. The new structure designed by the method can eliminate the influence of test noise, and more accurate MOS electric leakage can be obtained.

This disclosure provides a semiconductor test structure and its manufacturing method, relating to the field of semiconductor technology. The semiconductor test structure includes: a test array region, comprising a first array of active test regions arranged in an array, the angle between the extension direction of the first active test regions and a first direction being a preset angle, wherein two adjacent second active test regions located in different columns are connected to each other at a first boundary of the test array region along a second direction; and a plurality of test conductive line groups arranged along the first direction, wherein each test conductive line group includes two adjacent test conductive lines, each test conductive line extending along the second direction through the test array region, and the test conductive lines in the plurality of test conductive line groups are correspondingly coupled to the first active test regions, wherein the first ends of the two adjacent test conductive lines in each test conductive line group are electrically connected through interconnected second active test regions. This disclosure can improve the reliability and stability of test bit lines.

The application provides a semiconductor electrical property measurement structure, which comprises a test array, the test array comprises a plurality of test units, and the plurality of test units are arranged in a matrix, wherein the test unit comprises at least two transistors, and the plurality of transistors are electrically connected in sequence, adjacent transistors in the test unit share the same electrode; in the test array, the middle electrode of part of the test units is grounded, and the edge electrode serves as a first signal output end; the middle electrode of another part of the test units serves as a second signal output end, and the edge electrode is grounded; when the electrode of the transistor is in a high resistance state, the output current of the test unit is reduced, and the range of the reduction of the output current represents the type of the electrode in the high resistance state in the test unit. The application can monitor the distribution behavior of a small number of defective vias existing in a large number of dense vias, and locate the position of the defective via.

This invention provides a chip programming and testing array device, including a workbench. A support platform is provided on the surface of the workbench, and a support frame is fixedly connected to the surface of the workbench. An electric push rod is fixedly connected to the surface of the support frame, and a mounting plate is fixedly connected to the output end of the electric push rod. In this invention, the spring force firmly secures the first and second clips into the slot, thereby fixing the probe board. When the probe body needs to be replaced according to usage requirements, the first and second pressure plates on both sides of the clip block are pressed, causing the first and second clips to slide inside the clip block. The clip block is then removed from the mounting plate, making the probe board replacement operation simple and quick, eliminating the need for complex tools and lengthy debugging, significantly reducing the time spent replacing the probe board, and improving the conversion efficiency of the device for programming and testing different chips.

The invention provides a gradient magnetic field testing method and device for a magnetic shielding barrel. The gradient magnetic field testing device comprises a magnetic gradient testing unit, a supporting assembly and a connecting rod. An atom magnetometer can be nested in the magnetic gradient test unit to form a single magnetic field test unit. A plurality of magnetic gradient test units can be combined through the connecting rods to form a magnetic field gradient test array to adapt to the space in the shielding barrel. The magnetic field gradient test array can be connected with the supporting assembly, so that the magnetic field gradient test array is fixed in the shielding barrel and has mobility, and magnetic field distribution in the shielding barrel can be completely tested. According to the technical scheme, the technical problems that in the prior art, a visual large-range magnetic field imaging device is lacked, actual magnetic field gradient testing and compensation are lacked for a magnetic shielding barrel which is actually produced, processed and manufactured, and the space gradient in the magnetic shielding barrel can serve as an error term to be introduced into a magnetometer testing result are solved.

The utility model discloses a current test probe, can directly set up the one end of voltage needle with thorn with the measured object contact in the test, and the thorn is used for breaking the oxide film, makes the probe head and the battery pole post contact well. The elastic sheet has the elastic force of making the first fixed block and the second fixed block away, so that the probe head and the measured object contact, the probe head is connected with the test platform, and the test platform can show the current data and voltage data of the measured object. The elastic sheet has high reliability, is not easy to fatigue failure, can ensure the close contact between the probe head and the measured object, improves the measurement precision and data consistency, guarantees the long -term stable electrical connection, especially suitable for the test occasion of long -time continuous work, the elastic sheet is relatively short to spring length, reduces the overall size, is favorable to the construction denser test array, improves production efficiency, the elastic sheet is relatively simple to spring installation, simplifies the assembly process, when the elastic sheet is tired, is easy to replace, and the maintenance cost is reduced.

The invention provides a modularized multifunctional contact pressure anchoring test device and method, and the device is characterized in that a first positioning part on a positioning registration module is matched with a first positioning hole in a non-packaging sensor, and is matched with a second positioning hole in a signal switching system module; aligning each layer structure of the non-packaged sensor and the signal switching system module up and down, and aligning a contact of the signal switching system module with a test point of the non-packaged sensor; a second positioning piece on the positioning registration module is matched with a third positioning hole in the pressurization module and is matched with a fourth positioning hole in the non-packaged sensor, so that a pressurization array of the pressurization module is aligned with a test array of the non-packaged sensor; the signal transfer system module is connected with the non-packaged sensor and is connected with the multi-channel LCR tester; and the pressurizing module is used for pressurizing a test point of the non-packaged sensor. According to the invention, an accurate, efficient and repeatable pressure-capacitance signal anchoring test is provided for a non-packaged micro flexible pressure sensor array.

This invention provides a non-volatile memory and its automatic repair method, comprising: a main array for storing data and ECC check data; a test array; a read circuit for performing a read operation on the test array for each read operation on the main array; a refresh initiation circuit for counting the number of flipped bits in the test array based on the data read from the test array each time, determining whether the number of flipped bits is greater than or equal to a preset threshold, and if so, initiating a refresh operation on both the test array and the main array; and a write circuit for executing the refresh operation on both the test array and the main array. This invention can mitigate the impact of read interference rate.

The application relates to the technical field of electronic module testing, and discloses a serial testing method and system integrating multiple controllers and a storage medium. The method first extracts three types of independent testing modules, namely, a power supply testing module, a first communication testing module and a second communication testing module, from a testing device list, then establishes a time-sharing serial testing array comprising three time-sharing units, each time-sharing unit is provided with a time-sharing selection switch matrix, a plurality of controllers to be tested can be connected at the same time, and the three types of independent testing modules are respectively connected. Then, according to a time-sharing testing sequence instruction, each time-sharing unit is started and stopped in turn, the corresponding switches are turned on for testing, and the switches are turned off for non-testing, each time-sharing unit does not work at the same time, a first time length is set for waiting after power supply testing, a second time length is set for waiting after first communication testing, and the second time length is shorter than the first time length. The method realizes efficient utilization of testing module resources, improves the serial testing efficiency of multiple controllers, and guarantees the stability of the testing process and the accuracy of the testing result.

This invention provides a semiconductor process testing device, comprising: a substrate having a MOS device; wherein the gate of the MOS device is electrically connected to a first test node, the source of the MOS device is electrically connected to a second test node, and the body of the MOS device is electrically connected to a third test node; a bottom metal layer disposed on the substrate and electrically connected to the drain of the MOS device; a process test array disposed above the bottom metal layer; and a test interconnect structure disposed above the bottom metal layer, spaced apart from the process test array, electrically connected to the bottom metal layer, and electrically connected to a fourth test node. This invention can test the damage to the MOS device caused by the PID effect during the semiconductor device fabrication process, which helps in the optimization of semiconductor device processes and improves the performance of semiconductor devices.

Systems and methods for a digital pixel circuit for liquid crystal displays are provided. The design includes a dual-voltage pixel design, a two-transistor level-shift circuit design, self-adjusting transistor bias circuitry; and an optional on-chip test-array to determine die-specific design-center values for critical transistor leakage and threshold parameters. Level shift design simplicity, small pixel pitch, and applicability for small display applications such as microdisplays, are among the various benefits and advantages obtained.