38 results about "Test array" patented technology

The embodiment of the invention provides a transducer echo line sequence test method and a transducer echo line sequence test device, and the method comprises the steps: enabling a detection surface and a horizontal plane to form a first angle in an echo detection state, comparing waveform data of feedback signals obtained by reflecting the ultrasonic signals emitted by the plurality of test array elements through the detection surface with preset qualified data to determine a performance result of the transducer; in the line sequence detection state, a second angle is formed between the detection surface and the horizontal plane, and the actual flight time difference value of each adjacent test array element in the plurality of test array elements is determined according to waveform data of feedback signals obtained by reflecting ultrasonic signals emitted by the plurality of test array elements through the detection surface, and according to a comparison relation between a difference value between the actual flight time difference value and the theoretical flight time difference value and a preset threshold value, whether welding of each test array element is correct or not is determined. Therefore, an echo performance detection function and a multi-array element line sequence detection function can be integrated.

The embodiment of the invention provides a semiconductor test structure and a manufacturing method thereof, and the semiconductor test structure comprises a test array region which comprises test active regions arranged in an array. The plurality of test conductive wire groups are arranged along the first direction, each test conductive wire group comprises two test conductive wires which are adjacently arranged and a connecting part which is connected with the first ends of the two test conductive wires, each test conductive wire extends and penetrates through the test array area along a second direction, and the second direction is perpendicular to the first direction. And the at least one electric connection structure and the two external connection structures are located on the second ends of the test conductive wires in the plurality of test conductive wire groups, and the first ends and the second ends of the test conductive wires are opposite to each other. The at least one electric connection structure is electrically connected with the adjacent test conductive wires in the adjacent test conductive wire groups in the plurality of test conductive wire groups, and the two external connection structures are electrically connected with the two outermost test conductive wires in all the test conductive wires in the plurality of test conductive wire groups respectively.

The present application relates to high-voltage insulation gas humidity detection technical field, especially to a kind of high-voltage electrical equipment gas humidity detection circuit, method, device and storage medium, the present application method first obtains multiple test arrays;Then the multiple test arrays are respectively substituted into standard capacitance equation, obtain the standard capacitance estimated value of humidity sensor;Then according to the standard capacitance estimated value determine the deviation of standard capacitance application value, and when deviation is greater than deviation threshold, again through the standard capacitance equation obtains standard capacitance estimated value;Finally, according to the return value of humidity sensor, gas temperature and according to the standard capacitance estimated value selected humidity curve equation determines gas humidity.The present application embodiment selects corresponding humidity curve equation by the standard capacitance value determined to complete humidity detection, reduces the problem of inaccurate data caused by sensor drift.

A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

The utility model relates to the field of circuit board testing, in particular to a universal test fixture for a circuit board. The device comprises a universal base electrically connected with test equipment, the universal base is provided with a conversion module and an output module, the conversion module is electrically connected with the output module, the output module is detachably and fixedly provided with a test head assembly, and the test head assembly is electrically connected with the output module; when the circuit boards of different models need to be tested, the test array points on the output module are switched through the conversion module, and then the circuit boards of different models can be tested only by replacing the corresponding test head assemblies without additionally arranging jigs, so that time and labor are saved, and the cost is saved.

The application discloses a low-leakage on-chip interconnection signal line system and an addressable test array circuit, and relates to the technical field of solving the problem of leakage of interconnection signal lines. The low-leakage on-chip interconnection signal line system comprises interconnection signal lines and signal protection channels which can be configured to have equal voltages, wherein the signal protection channels comprise: a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnection signal lines in the vertical projection direction of a chip, and the interconnection signal lines are located between the first shielding layer and the second shielding layer; a first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer respectively, and the interconnection signal lines are located between the first shielding wall and the second shielding wall.

The invention provides an automatic test system for vehicle-mounted software, and the system comprises a test case management unit which is used for determining a to-be-executed target test case and sending the target test case to a compiling unit, and the target test case comprises a target test code file and a target configuration file; the compiling unit is used for compiling the target test code file and a source code file involved in the target test code according to the target configuration file to obtain an executable file corresponding to the target test case; the execution unit is used for executing the executable file after establishing connection with the vehicle-mounted controller installed with the vehicle-mounted software, reading an actual execution result of the test variable from a test array pre-established by the vehicle-mounted controller, and feeding back the actual execution result to the test case management unit; and the test case management unit is used for comparing the actual execution result of the test variable with the expected execution result to determine a test result for the test variable.

The application provides a system, electronic equipment and storage medium for continuous testing of array devices, comprising a first host computer and a probe station; the first host computer sends a scanning path to the probe station to control the probe station to perform scanning test on a to-be-tested array device; a tray of the probe station moves according to path points set by the scanning path, reaches a specified position, then moves the tray upward to connect a probe and an electrode of the to-be-tested array device, and the to-be-tested array device is tested by an electronic testing device according to a test instruction sent by a second host computer, and the above process is repeated until all electrodes of the to-be-tested array device are tested. Scanning test of any test parameter can be realized on any array device, and then data visualization is performed in combination with a detection position coordinate and a test result of the position, thereby providing comprehensive and effective test data for array devices of different shapes.

The invention provides a method for carrying out color carving on metal, which comprises the following steps: selecting a processing mode, and starting red light carving; laser head focusing is completed, and the positive focus height is fed back; setting an initial height according to the focal height, and sequentially increasing the height of a laser head according to a fixed height difference so as to obtain a plurality of ColorID; selecting a corresponding ColorID of a second test material, and descending or ascending the laser head to a corresponding height; processing and generating a corresponding material test color contrast matrix by setting parameters of the second material test array; setting engraving parameters of the to-be-processed material, and processing the material. When laser heads are offset in focus, different in distance and different in height, generated energy is different, namely different temperatures are generated, different colors are formed after the energy reacts with metal, and then different colors can be carved on the metal. On the basis of offset focus of a laser head, different powers and speeds are set for a processing image, so that colors can be controllably printed on metal.

The invention discloses a pharmacodynamic test method for a cough relieving mixture, which comprises the following steps: constructing four core pharmacodynamic test sub-models containing ammonia water to cause young mouse cough, citric acid to cause young guinea pig cough, rabbit in-vitro trachea cilia mucus movement and young mouse trachea phenol red excretion and a body model of a test result analysis sub-model; each pharmacodynamic test sub-model is provided with a plurality of groups of test arrays and test individuals; pathogen data is imported to generate a simulated disease scene, and a corresponding drug sequence is called to intervene and collect physiological index change data; and multi-dimensional pharmacodynamic parameters are evaluated through the analysis sub-model, and a dose-effect relation curve and an evaluation report are generated. According to the invention, a parallel verification system for antitussive and expectorant tests is formed, the antitussive effective dose, the expectorant effective dose and the effective dose range under the dual action of the medicine are determined through multi-model cross validation, the accuracy degree of judging the effectiveness of the medicine is greatly improved, and a reliable method support is provided for evaluating the efficacy of the cough-stopping mixture.

The invention relates to an electrical property test structure and a test method thereof, and relates to the technical field of integrated circuits, the structure comprises a test array which comprises a target transistor and a plurality of peripheral areas surrounding the target transistor and distributed along the radial direction of the test array, and the test array is configured to receive a test voltage according to the received test voltage; outputting the to-be-measured current generated by the target transistor and / or the plurality of peripheral regions; the gating device is connected with the target transistor and the plurality of peripheral areas and is configured to respond to a received gating signal, and at least one peripheral area is connected with the target transistor; and / or connecting the plurality of peripheral regions to adjust the current to be tested generated by the test array; wherein the test array comprises to-be-tested current of the peripheral area, and the to-be-tested current is in proportional relation with to-be-tested current only comprising the target transistor. The structure and the method are completely compatible with the existing processing technology, and are suitable for platforms with different technical nodes. The new structure designed by the method can eliminate the influence of test noise, and more accurate MOS electric leakage can be obtained.

The present application relates to a semiconductor test structure. The semiconductor test structure includes: a first test circuit, a second test circuit, a third test circuit, and a fourth test circuit that are sequentially connected end to end to form a circular closed circuit; a plurality of diodes, respectively connected between adjacent test circuits; a first test array and a second test array, the first test array and the second test array both including a plurality of test units spaced apart along a first direction; the test units each including a multi-layer spaced apart metal layer, a dielectric layer, and a conductive plug. The semiconductor test structure of the present application, by providing a first test array and a second test array and adding diodes, can simultaneously detect the reliability of the dielectric layer between the conductive plugs corresponding to two adjacent parallel metal layers and the reliability of the dielectric layer between the conductive plug located at the end of the metal layer and the metal layer adjacent in the second direction.

This disclosure provides a semiconductor test structure and its manufacturing method, relating to the field of semiconductor technology. The semiconductor test structure includes: a test array region, comprising a first array of active test regions arranged in an array, the angle between the extension direction of the first active test regions and a first direction being a preset angle, wherein two adjacent second active test regions located in different columns are connected to each other at a first boundary of the test array region along a second direction; and a plurality of test conductive line groups arranged along the first direction, wherein each test conductive line group includes two adjacent test conductive lines, each test conductive line extending along the second direction through the test array region, and the test conductive lines in the plurality of test conductive line groups are correspondingly coupled to the first active test regions, wherein the first ends of the two adjacent test conductive lines in each test conductive line group are electrically connected through interconnected second active test regions. This disclosure can improve the reliability and stability of test bit lines.

A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. one of the cells which is coupled to one of the first input pads and one of the second input pads is turned on, and a current flowing through the turned-on cell is measured.

The invention discloses a transistor variability test characterization method, device and equipment, relates to the technical field of semiconductor characterization and test, and is used for fitting the variability of a device in high sigma distribution. Comprising the following steps: determining a plurality of to-be-tested devices in a test array; applying electric stress to the plurality of to-be-tested devices in the test array and testing to obtain test experiment data; on the basis of test experiment data, statistical distribution of device parameters changing along with time is constructed; and fitting the statistical distribution by using the statistical model to obtain a fitting model so as to complete time domain variability test analysis and model fitting. According to the technical scheme provided by the invention, the reliability and variability of a large number of semiconductor devices can be efficiently tested in batches, the test efficiency and the data statistics significance are remarkably improved, and the statistical distribution of device parameters drifting along with time is accurately described; the finally obtained fitting model can predict the variability and reliability of the semiconductor device more accurately.

Embodiments disclosed herein provide cooling for a test array (e.g., a semiconductor test array) using a 2-phase refrigerant. Testing can be performed without any added insulation, which improves test site density significantly. The refrigerant can be provided by any suitable refrigerant source, such as a pump or valve-controlled pressure chamber, for example, and can be provided to a cold plate of a test site, for example. The cold plate can include a flow field or flow channels for guiding the refrigerant to evenly cool surfaces and / or prevent condensation forming on outer surfaces of the cold plate or test site.

The disclosure provides a visual evoked working memory evaluation system and method, which can be applied to the fields of neuroscience technology and computer vision technology. The system comprises: a control device configured to execute multiple rounds of display tasks, wherein the (i-1)th round of display tasks is controlled to display a memory array image, a gray scale stimulus image and a test array image based on the (i-1)th task intensity parameter and the (i-1)th stimulus intensity parameter; an interaction device configured to determine the (i-1)th feedback result in response to the (i-1)th feedback operation of a target object during the execution of the (i-1)th round of display tasks; and an evaluation device configured to determine the (i-1)th working memory capacity evaluation result based on the (i-1)th feedback result, and determine the (i)th task intensity parameter and the (i)th stimulus intensity parameter based on the (i-1)th feedback result and the (i-1)th working memory capacity evaluation result to obtain the (i)th round of display tasks.

The application provides a semiconductor electrical property measurement structure, which comprises a test array, the test array comprises a plurality of test units, and the plurality of test units are arranged in a matrix, wherein the test unit comprises at least two transistors, and the plurality of transistors are electrically connected in sequence, adjacent transistors in the test unit share the same electrode; in the test array, the middle electrode of part of the test units is grounded, and the edge electrode serves as a first signal output end; the middle electrode of another part of the test units serves as a second signal output end, and the edge electrode is grounded; when the electrode of the transistor is in a high resistance state, the output current of the test unit is reduced, and the range of the reduction of the output current represents the type of the electrode in the high resistance state in the test unit. The application can monitor the distribution behavior of a small number of defective vias existing in a large number of dense vias, and locate the position of the defective via.

This invention provides a chip programming and testing array device, including a workbench. A support platform is provided on the surface of the workbench, and a support frame is fixedly connected to the surface of the workbench. An electric push rod is fixedly connected to the surface of the support frame, and a mounting plate is fixedly connected to the output end of the electric push rod. In this invention, the spring force firmly secures the first and second clips into the slot, thereby fixing the probe board. When the probe body needs to be replaced according to usage requirements, the first and second pressure plates on both sides of the clip block are pressed, causing the first and second clips to slide inside the clip block. The clip block is then removed from the mounting plate, making the probe board replacement operation simple and quick, eliminating the need for complex tools and lengthy debugging, significantly reducing the time spent replacing the probe board, and improving the conversion efficiency of the device for programming and testing different chips.

The present invention discloses a calibration device and method for a broadband digital phased array antenna suitable for cylindrical conformal. The device includes a calibration track, a conformal calibration frame, a microstrip antenna, a calibration chassis and an electric tractor. The conformal calibration frame is installed on the calibration track. The output of the calibration chassis is connected to the driving end of the electric tractor, and the electric tractor is used to drive the conformal calibration frame to slide on the calibration track. A plurality of calibration antennas are installed on the conformal calibration frame. The connection lines between the calibration antennas and the to-be-tested array elements are parallel to the normal directions of the to-be-tested array elements. The distances between each calibration antenna and each to-be-tested array element meet the antenna near-field test conditions. The microstrip antenna is deployed between two adjacent to-be-tested array elements, and the deployment direction is parallel to the moving direction of the conformal calibration frame. One end of the microstrip antenna is connected to a matching load, and the other end is connected to the calibration chassis through a microstrip line switch power divider. The calibration antenna is connected to the calibration chassis through a calibration frame switch power divider. The present invention can realize the calibration of the conformal digital broadband phased array antenna.

The invention provides a semiconductor electrical property measurement structure, which comprises a test array, the test array comprises a plurality of test units, the plurality of test units are distributed in a matrix, each test unit comprises at least two transistors, the plurality of transistors are electrically connected in sequence, and in the test units, adjacent transistors share the same electrode; in the test array, the middle electrodes of part of the test units are grounded, the edge electrodes serve as first signal output ends, the middle electrodes of the other part of the test units serve as second signal output ends, and the edge electrodes are grounded; when the electrode of the transistor is in a high-resistance state, the output current of the test unit is reduced, and the decreasing amplitude range of the output current represents the type of the electrode in the high-resistance state in the test unit. According to the invention, the distribution behavior of a small number of defective via holes in a large number of dense via holes can be monitored, and the positions of the defective via holes can be positioned.

The invention relates to an addressable test circuit and method for the reliability of a subsequent process, and the circuit comprises an addressing circuit which is used for receiving a binary address signal, decoding the binary address signal, and generating a plurality of gating signals; a switching circuit connected with the addressing circuit and configured to selectively transmit an input test signal to a corresponding output line in response to the gating signal; the to-be-tested array comprises a plurality of to-be-tested units, and each to-be-tested unit is connected to one output line of the switching circuit so as to receive the input test signal; the unit to be tested comprises a metal interconnection layer; in the testing process, the failure mode or the design parameter critical value of the metal interconnection structure is judged through the input testing signal and the output signal obtained from the unit to be tested. According to the method, the process optimization efficiency can be improved, the failure can be directly positioned to the specific level and structure, large-scale DOE trial and error are reduced, and the research and development iteration and yield climbing period is shortened.

The utility model relates to the technical field of camera module testing, in particular to a test graphic card, which is used for testing an array camera module and comprises a rectangular test surface which comprises a transverse datum line, a longitudinal datum line and a plurality of test units distributed in an array mode. The test unit is rectangular and is internally provided with a feature mark; the diagonal line of the test unit is a full field of view which can be shot by a single camera module, and the test unit is provided with four feature marks on each of the 0.5 field of view and the 0.92 field of view; wherein along the direction of the transverse reference line, partial feature marks of the adjacent test units on the 0.92 field of view coincide; in the direction of the longitudinal reference line, part of the feature marks of the adjacent test units in the 0.5 view field and the 0.92 view field coincide, so that the aliasing phenomenon of the feature marks on the adjacent test units is avoided, and the definition difference of the image edges of the test units shot by a single camera module is further avoided; further, the image direction is caused to the splicing and the array camera module cannot be tested.

The invention discloses a wind turbine generator wind wheel imbalance fault diagnosis method and a related device, and the method comprises the steps: obtaining wind wheel rotation frequency amplitudes in a preset period under the condition that a wind turbine generator is in a grid-connected power generation state, and sequentially putting the wind wheel rotation frequency amplitudes into a wind wheel imbalance change trend detection array according to a time sequence, when a preset period is larger than a wind wheel imbalance change trend long-period threshold value, under the condition that a wind wheel imbalance change trend abnormity suspicion condition is met, wind wheel imbalance change trend abnormity long-period fault diagnosis is carried out through a trend detection method; and when the preset period is smaller than a short-period threshold value of the wind wheel imbalance variation trend, drawing a wind wheel rotation frequency amplitude cumulative deviation curve according to the cumulative deviation of each wind wheel rotation frequency amplitude relative to a historical wind wheel rotation frequency target amplitude, so as to carry out abnormal short-time fault diagnosis on the wind wheel imbalance variation trend. The method not only can capture the trend enhancement characteristics with a long period, but also can keep sensitive to the abnormity of instantaneous sudden increase, and effectively avoids late report and missing report of early faults.

The invention provides a gradient magnetic field testing method and device for a magnetic shielding barrel. The gradient magnetic field testing device comprises a magnetic gradient testing unit, a supporting assembly and a connecting rod. An atom magnetometer can be nested in the magnetic gradient test unit to form a single magnetic field test unit. A plurality of magnetic gradient test units can be combined through the connecting rods to form a magnetic field gradient test array to adapt to the space in the shielding barrel. The magnetic field gradient test array can be connected with the supporting assembly, so that the magnetic field gradient test array is fixed in the shielding barrel and has mobility, and magnetic field distribution in the shielding barrel can be completely tested. According to the technical scheme, the technical problems that in the prior art, a visual large-range magnetic field imaging device is lacked, actual magnetic field gradient testing and compensation are lacked for a magnetic shielding barrel which is actually produced, processed and manufactured, and the space gradient in the magnetic shielding barrel can serve as an error term to be introduced into a magnetometer testing result are solved.

The utility model discloses a current test probe, can directly set up the one end of voltage needle with thorn with the measured object contact in the test, and the thorn is used for breaking the oxide film, makes the probe head and the battery pole post contact well. The elastic sheet has the elastic force of making the first fixed block and the second fixed block away, so that the probe head and the measured object contact, the probe head is connected with the test platform, and the test platform can show the current data and voltage data of the measured object. The elastic sheet has high reliability, is not easy to fatigue failure, can ensure the close contact between the probe head and the measured object, improves the measurement precision and data consistency, guarantees the long -term stable electrical connection, especially suitable for the test occasion of long -time continuous work, the elastic sheet is relatively short to spring length, reduces the overall size, is favorable to the construction denser test array, improves production efficiency, the elastic sheet is relatively simple to spring installation, simplifies the assembly process, when the elastic sheet is tired, is easy to replace, and the maintenance cost is reduced.

The invention provides a modularized multifunctional contact pressure anchoring test device and method, and the device is characterized in that a first positioning part on a positioning registration module is matched with a first positioning hole in a non-packaging sensor, and is matched with a second positioning hole in a signal switching system module; aligning each layer structure of the non-packaged sensor and the signal switching system module up and down, and aligning a contact of the signal switching system module with a test point of the non-packaged sensor; a second positioning piece on the positioning registration module is matched with a third positioning hole in the pressurization module and is matched with a fourth positioning hole in the non-packaged sensor, so that a pressurization array of the pressurization module is aligned with a test array of the non-packaged sensor; the signal transfer system module is connected with the non-packaged sensor and is connected with the multi-channel LCR tester; and the pressurizing module is used for pressurizing a test point of the non-packaged sensor. According to the invention, an accurate, efficient and repeatable pressure-capacitance signal anchoring test is provided for a non-packaged micro flexible pressure sensor array.

This invention provides a non-volatile memory and its automatic repair method, comprising: a main array for storing data and ECC check data; a test array; a read circuit for performing a read operation on the test array for each read operation on the main array; a refresh initiation circuit for counting the number of flipped bits in the test array based on the data read from the test array each time, determining whether the number of flipped bits is greater than or equal to a preset threshold, and if so, initiating a refresh operation on both the test array and the main array; and a write circuit for executing the refresh operation on both the test array and the main array. This invention can mitigate the impact of read interference rate.

The present invention discloses a laser radar-based pedestrian trajectory prediction model testing method and system, wherein the method includes the following steps: using a laser radar to detect 3D targets in a selected real environment and filter pedestrian data; matching the perceived pedestrians using a multi-target tracking algorithm to construct a two-dimensional target tracking array; performing a frame extraction operation on the two-dimensional pedestrian target tracking array according to the input frame spacing of the model to be tested to obtain a sampling array; performing data completion on the sampling array to obtain a test array; sorting the test array corresponding to each pedestrian in a certain order to obtain a pedestrian trajectory data file; inputting the pedestrian trajectory data file into the pedestrian trajectory prediction model to be tested; comparing the predicted results with the pedestrian trajectory true value, and evaluating the accuracy and real-time performance of the model. This invention can improve the reliability of the performance testing of pedestrian trajectory prediction models before application in real environments.

The embodiment of the present invention discloses a parameter linkage rule conversion test method, a ventilator and a storage medium. A parameter linkage rule conversion test method is applied to a ventilator, and the method includes: listing all parameter linkage rules; converting each parameter linkage rule in turn to determine the calculation formula corresponding to the parameter linkage rule; determining the parameter linkage list of the current parameter linkage rule according to the calculation formula and the Excel function; selecting a test array through a boundary value analysis method; performing a parameter linkage defect test based on the consistency of the control parameters in the test array and the parameter linkage list to obtain the test results. The present invention converts ideas for complex parameter linkage rules and can improve the efficiency of parameter linkage testing. Determine the parameter linkage list according to the calculation formula and the Excel function, increase the coverage of the parameter linkage test, reduce labor costs, and then perform parameter linkage defect testing to provide comprehensive protection for the stability and security of the system.