6 results about "Test array" patented technology

The application discloses a low-leakage on-chip interconnection signal line system and an addressable test array circuit, and relates to the technical field of solving the problem of leakage of interconnection signal lines. The low-leakage on-chip interconnection signal line system comprises interconnection signal lines and signal protection channels which can be configured to have equal voltages, wherein the signal protection channels comprise: a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnection signal lines in the vertical projection direction of a chip, and the interconnection signal lines are located between the first shielding layer and the second shielding layer; a first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer respectively, and the interconnection signal lines are located between the first shielding wall and the second shielding wall.

This invention provides a chip programming and testing array device, including a workbench. A support platform is provided on the surface of the workbench, and a support frame is fixedly connected to the surface of the workbench. An electric push rod is fixedly connected to the surface of the support frame, and a mounting plate is fixedly connected to the output end of the electric push rod. In this invention, the spring force firmly secures the first and second clips into the slot, thereby fixing the probe board. When the probe body needs to be replaced according to usage requirements, the first and second pressure plates on both sides of the clip block are pressed, causing the first and second clips to slide inside the clip block. The clip block is then removed from the mounting plate, making the probe board replacement operation simple and quick, eliminating the need for complex tools and lengthy debugging, significantly reducing the time spent replacing the probe board, and improving the conversion efficiency of the device for programming and testing different chips.

The utility model discloses a current test probe, can directly set up the one end of voltage needle with thorn with the measured object contact in the test, and the thorn is used for breaking the oxide film, makes the probe head and the battery pole post contact well. The elastic sheet has the elastic force of making the first fixed block and the second fixed block away, so that the probe head and the measured object contact, the probe head is connected with the test platform, and the test platform can show the current data and voltage data of the measured object. The elastic sheet has high reliability, is not easy to fatigue failure, can ensure the close contact between the probe head and the measured object, improves the measurement precision and data consistency, guarantees the long -term stable electrical connection, especially suitable for the test occasion of long -time continuous work, the elastic sheet is relatively short to spring length, reduces the overall size, is favorable to the construction denser test array, improves production efficiency, the elastic sheet is relatively simple to spring installation, simplifies the assembly process, when the elastic sheet is tired, is easy to replace, and the maintenance cost is reduced.

This invention provides a non-volatile memory and its automatic repair method, comprising: a main array for storing data and ECC check data; a test array; a read circuit for performing a read operation on the test array for each read operation on the main array; a refresh initiation circuit for counting the number of flipped bits in the test array based on the data read from the test array each time, determining whether the number of flipped bits is greater than or equal to a preset threshold, and if so, initiating a refresh operation on both the test array and the main array; and a write circuit for executing the refresh operation on both the test array and the main array. This invention can mitigate the impact of read interference rate.

The application relates to the technical field of electronic module testing, and discloses a serial testing method and system integrating multiple controllers and a storage medium. The method first extracts three types of independent testing modules, namely, a power supply testing module, a first communication testing module and a second communication testing module, from a testing device list, then establishes a time-sharing serial testing array comprising three time-sharing units, each time-sharing unit is provided with a time-sharing selection switch matrix, a plurality of controllers to be tested can be connected at the same time, and the three types of independent testing modules are respectively connected. Then, according to a time-sharing testing sequence instruction, each time-sharing unit is started and stopped in turn, the corresponding switches are turned on for testing, and the switches are turned off for non-testing, each time-sharing unit does not work at the same time, a first time length is set for waiting after power supply testing, a second time length is set for waiting after first communication testing, and the second time length is shorter than the first time length. The method realizes efficient utilization of testing module resources, improves the serial testing efficiency of multiple controllers, and guarantees the stability of the testing process and the accuracy of the testing result.

This invention provides a semiconductor process testing device, comprising: a substrate having a MOS device; wherein the gate of the MOS device is electrically connected to a first test node, the source of the MOS device is electrically connected to a second test node, and the body of the MOS device is electrically connected to a third test node; a bottom metal layer disposed on the substrate and electrically connected to the drain of the MOS device; a process test array disposed above the bottom metal layer; and a test interconnect structure disposed above the bottom metal layer, spaced apart from the process test array, electrically connected to the bottom metal layer, and electrically connected to a fourth test node. This invention can test the damage to the MOS device caused by the PID effect during the semiconductor device fabrication process, which helps in the optimization of semiconductor device processes and improves the performance of semiconductor devices.