Test method and device of memory

A technology for memory testing and memory, applied in static memory, instruments, etc., can solve problems such as inaccurate results, lower reliability of test results, inaccurate response to circuit temperature distribution, etc., to achieve simple procedures and accurate reliability test results , low cost effect

Active Publication Date: 2012-05-23
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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Problems solved by technology

Therefore, in the process of applying high voltage, only the electrical performance failure of the circuit is considered, and the influence of heat generated by the power consumption of the circuit itself is not considered, and the result is inaccurate
In addition, the high temperature applied externally cannot accurately reflect the temperature distribution of the circuit itself, which is related to the thermal conductivity of the circuit and the temperature control capability of the aging furnace
As the density of memory gradually increases, memory (especially flash memory) has developed in the direction of 3D, and the aging furnace of high-temperature aging test cannot reflect the real temperature distribution of the circuit under test, and the reliability of the test results obtained is greatly reduced. reduce

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  • Test method and device of memory

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Embodiment Construction

[0031] The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0032] The temperature of the existing burn-in test cannot be accurately controlled, the internal temperature distribution of the circuit under test is uneven, and the test result error caused by only considering factors such as electrical properties is large, and with the change of the structure of the memory, the existing burn-in furnace cannot Well adapted to problems such as, the present invention provides a kind of test method of memory, specifically as follows:

[0033] The controller sends out a test command, so that the array under test of the memory is in a test state;

[0034] After the signal generator receives the test command, it generates the corresponding test signal;

[0035] After the actuator receives the test signal, it is input into the array under test to make the array under test generate power consumption a...

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Abstract

The invention discloses a test method of a memory, which comprises the following steps that: a controller issues a test command, so that a tested array of the memory is in a test state; after a signal generator receives the test command, a corresponding test signal is generated; after an actuator receives the test signal, the test signal is inputted into the tested array; the tested array generates the power consumption to form the test temperature required by the test of the tested array, so that a test result is obtained, i.e. an aging test is carried out by the temperature generated by the self power consumption of the tested array, and the tested array is not required to be externally heated, thereby the situations that test errors are produced by the inaccurate control of external temperature, the nonuniform distribution of internal temperature, only the self power consumption of the tested array is considered, the test errors caused by power consumption of the tested array is not considered and other factors are avoided, and the memory has more accurate reliability test result, simpler processes and lower cost.

Description

technical field [0001] The invention relates to a memory testing method, in particular to a memory reliability testing method and device. Background technique [0002] According to the statistical results, the distribution of faults in the life cycle of integrated circuit products can be expressed by a bathtub curve, such as figure 1 shown. Among them, the horizontal axis represents the working time of integrated circuit products, and the vertical axis represents the failure rate, from figure 1 It can be seen that most of the failures of integrated circuit products occur within a period of initial work, mainly due to defects in the circuit manufacturing process, and the failure rate is very high. Burn-in testing is an important means to speed up IC products through this period. Its principle is to apply a certain overstress (high temperature or high voltage) to the integrated circuit, so that some early faults of the circuit, such as electron migration, hot carrier degrad...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/08
Inventor 李崇仁刘平查锦崔小乐
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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