Testing array and method for testing storage array
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An array and pair test technology, which is applied in the field of test arrays and test storage arrays, can solve the problems of inaccurate small-scale testing and inability to replicate load effect setup time, etc.
Inactive Publication Date: 2003-04-30
HEWLETT PACKARD CO
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This technique may be unsatisfactory because small-scale tests cannot replicate loading effects, settling times, and other phenomena that occur in full-scale arrays
Therefore, small-scale testing may not be accurate enough for some applications
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[0019] Test arrays and methods of testing arrays will be discussed with preferred implementations and pictures.
[0020] figure 1 is a simplified diagram of a test array 100 according to a first embodiment. The test array 100 includes a plurality of row conductors 110 and column conductors 120 . The row conductor 110 intersects the column conductor 120 at the memory cell 130 . The test array 100 is an intersection memory array, which can be any intersection memory type, for example: magnetic random access memory (MRAM), fuse memory (fuse memory), anti-fuse memory (anti-fuse memory), charge memory, mask Read-only (mask ROM) memory and other storage types.
[0021] The row conductors 110 of the test array 100 terminate at conductive terminals 112 and the column conductors 120 terminate at conductive terminals 122 . figure 1 , endpoints 112, 122 are illustrated as conductive pads. However, any form of conductive terminals is suitable for use with test array 100 . Endpoints ...
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Abstract
A test array (100, 200) includes row conductors (110, 210), column conductors (120, 220), and memory cells (130, 230) located at crossing points of the row and column conductors. The test array (100, 200) can have groups (124, 214, 224) of the row conductors (110, 210) or the column conductors (120, 220) electrically coupled, or ganged together, so that they share common terminals (216, 226). Other selected row and column conductors can have individual terminals (112, 122, 212, 222). In this configuration, memory cells (130, 230) located at the intersection of row and column conductors that have individual terminals (112, 122, 212, 222) can have their characteristics measured using a test apparatus. Ganging together groups of row or column conductors means that the test array has (100, 200) fewer terminals for connection to the test apparatus. Therefore, a test apparatus having a limited number of probes for connection to test array terminals can be used to test arrays (100, 200) of various sizes.
Description
technical field [0001] The present invention relates to testing arrays and methods of testing storage arrays. More specifically, the present invention relates to testing methods and arrays that allow accurate testing of the arrays without unnecessary time and expense. Background technique [0002] Intersection memory arrays contain memory cells located at the intersections of horizontal row conductors and vertical column conductors. A memory cell acts as a memory element in a cross-point memory array, typically storing a binary state "1" or "0". Memory cells, row and column conductors, and other circuitry can be placed on the substrate. Well-known examples of cross-point memory arrays include non-volatile memories, such as one-time-programmable (OTP) memories, and reprogrammable memories. Storage arrays need to be tested in many environments, such as before mass production and during the development of new storage arrays. Testing may include measuring characteristics of ...
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