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Middle of line structures

A gate structure and source technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc.

Active Publication Date: 2019-07-23
格芯美国公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This loss of sidewall material will expose the metal material in the gate structure, causing a short circuit between the metal material in the gate structure and the metal material itself used to form the contact

Method used

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  • Middle of line structures
  • Middle of line structures
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Embodiment Construction

[0017] The present disclosure relates generally to semiconductor structures, and more particularly, to mid-end-of-line structures and fabrication methods. In an embodiment, the methods and structures provided herein use spacers on the sides of the gate structure to prevent shorting of the source / drain (S / D) contacts to the metallization of the gate structure. Advantageously, the spacers will provide additional material to prevent short circuits during the fabrication process, ie during the formation of the interconnect structures for the source / drain contacts. The structures provided herein also provide gate structures with improved low parasitic capacitance.

[0018] The structures of the present disclosure can be fabricated in a variety of ways using a variety of different tools. In general, methods and tools are used to form structures with micron and nanometer dimensions. The methods, ie, techniques, for fabricating the structures of the present disclosure have been adop...

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PUM

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Abstract

The invention relates to middle of line structures. The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and / or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and / or drain metallization features, and separated from the gate structures by the spacers.

Description

technical field [0001] The present disclosure relates generally to semiconductor structures, and more particularly, to mid-end-of-line structures and fabrication methods. Background technique [0002] As semiconductor processes continue to shrink, eg, scale, the desired spacing between features (ie, pitch) also gets smaller. To this end, in smaller technology nodes, fabrication such as back-end-of-line (BEOL) and mid-line-of-line (MOL) metallization of interconnects due to critical dimension (CD) scaling and processing capabilities and materials used to fabricate such structures Characterization becomes even more difficult. [0003] For example, in order to fabricate interconnect structures for source and drain contacts, it is necessary to remove dielectric material adjacent to the gate structure. The removal of this dielectric material is provided by an etching process which also tends to attack the spacer material in the gate structure. That is, the low-k dielectric mat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/088H01L21/8234
CPCH01L27/088H01L21/823468H01L21/823475H01L29/66545H01L29/66575H01L21/76897H01L21/76831H01L21/7682H01L21/76865H01L23/485H01L21/76883H01L21/28079H01L21/28088H01L21/31144H01L21/76804H01L21/76816H01L29/41775
Inventor 臧辉许国伟K·塔巴克曼V·萨尔德赛
Owner 格芯美国公司