DAC error measurement method and device

Abstract

The invention discloses a DAC error measurement method and device, and the device comprises an ADC and a feedback DAC, wherein the measurement input of the ADC comprises a square wave signal with a fixed frequency, a DC signal with a fixed logic level, and the analog output of the feedback DAC; a measurement selection module which is used for providing measurement digits in the digital output forthe independently selected source unit and providing residual digits of the digital output for the residual source unit, wherein the measurement digits are reversible digits, and the residual digits are non-reversible digits; and a measuring module which is used for measuring the amplitude of the digital output according to the digital output. One path of overturning number in the digital output is a measuring number, the remaining numbers are non-flipping numbers, and then the measurement selection module can independently select one source unit to receive the measurement number, matching errors of other source units are not introduced into the selected source unit during error measurement, and error measurement is carried out under the same bias condition due to the fact that the direct-current signal is a constant level, so that the error measurement precision is improved.

Description

Technical field [0001] This application relates to the field of communication technology, and in particular to a method and device for measuring DAC errors. Background technique [0002] The analog-to-digital converter (ADC) based on the delta-sigma modulator (DSM) structure has a wide range of applications in the communication and audio fields, and is the best alternative for high-precision ADCs . [0003] The DSM is composed of a loop filter (Loop Filter, LF for short), a quantizer (Q for short), and a digital-to-analog converter (DAC). The signal-to-quantization-noise ration (SQNR) is determined by the order of the loop filter and the number of bits of the quantizer. The higher the order and the number of bits, the higher the SNQR and the better the performance of DSM. Good, but the circuit complexity is also greater. In order to balance DSM performance and circuit complexity, the order of the loop filter is generally 3 or 4, and the number of bits of the quantizer is 4 bits....

AI Technical Summary

Problems solved by technology

[0004] Compared with the 1-bit quantizer, the 4-bit quantizer brings a problem: the mismatch of the feedback DAC will deteriorate the linearity of the modulator, especially the DAC of the outermost loop

In the DAC error measurement circuit, when a complex signal excitation source is used, such as a rail-to-rail oscillation signal, the complexity of the DAC error measurement circuit will be increased. When a simple signal excitation source is used, such as a DC signal excitation source, it can be reduced. Small circuit complexity, but there are differences in the measurement parameters of each measurement, such as different comparators used when measuring different current units, resulting in unsatisfactory measurement accuracy

[0006] In summary, the existing DAC error measurement circuit has the technical problem of unsatisfactory measurement accuracy

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