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Redundant processor architecture

A technology of a processor and management organization, applied in the direction of fault handling not based on redundancy, error detection of data for data redundancy in hardware, electrical digital data processing, etc.

Active Publication Date: 2019-08-30
ZF FRIEDRICHSHAFEN AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, components that perform safety-critical functions cannot be deactivated

Method used

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  • Redundant processor architecture

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Embodiment Construction

[0034] according to figure 1 The multiprocessor system 101 has a first processor 103 and a second processor 105 . Both processors 103, 105 have multiple cores. Thus, the first processor 103 has a first core 107 , a second core 109 , a third core 111 and a supervisory authority 113 . Accordingly, the second processor 105 has a first core 115 , a second core 117 , a third core 119 and a management mechanism 121 .

[0035] The first sensor signal 123 is applied to the first core 107 of the first processor 103 and to the first core 115 of the second processor 105 . The second sensor signal 125 is applied to the second core 109 of the first processor 103 and to the first core 115 of the second processor 105 . First sensor signal 123 and second sensor signal 125 are based on redundant measurements of a single physical variable by means of two different sensors.

[0036]The third sensor signal 127 is similarly applied to the second core 117 of the second processor and to the thir...

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Abstract

The invention relates to an assembly (101) with a first processor (103) and a second processor (103); wherein the first processor (103) has a first core (107), a second core (109), and a control entity (113); the second processor (105) has a first core (115); and the first core (107) and the second core (109) of the first processor (103) and the first core (115) of the second processor (105) are designed to carry out a first procedure. The control entity (113) of the first processor (103) is designed to carry out the following steps: comparing the result of carrying out the first procedure onthe first core (107) of the first processor (103) with the result of carrying out the first procedure on the second core (109) of the first processor (103); and comparing the result of carrying out the first procedure on the first core (107) of the first processor (103) and the result of carrying out the first procedure on the second core (109) of the first processor (103) with the result of carrying out the first procedure on the first core (115) of the second processor (105) if the results of carrying out the first procedure on the first core (107) and the second core (109) of the first processor (103) deviate from each other.

Description

technical field [0001] The invention relates to a device according to the preamble of claim 1 and a method according to claim 10 . Background technique [0002] The multiprocessor architectures known from the prior art are only limitedly suitable for meeting the future requirements imposed by autonomous vehicles. Especially when ASIL-D specifications need to be applied, it is very difficult to meet the requirements of the standard ISO 26262-1. [0003] A common solution for systems implementing operational safety consists in monitoring components of the system and deactivating them in the event of a fault. However, components that implement safety-critical functions cannot be deactivated. Systems with safety-critical functions must be fault-tolerant and ensure that the safety-critical functions can also be implemented in the event of a fault. Fault-tolerant systems known from the prior art are described in the article by C. Temple and A. Vilela in Elektroniknet, July 2014...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/16G06F11/18
CPCG06F11/1641G06F11/181G06F11/184G06F11/0724G06F11/0751G06F11/0793G06F11/1629G06F11/165
Inventor 比伦特·萨里
Owner ZF FRIEDRICHSHAFEN AG