Method and device for realizing S box in SM4 algorithm

An algorithm and multiplication technology, which is applied in the field of realization of S-box in SM4 algorithm, can solve problems such as multi-circuit area, S-box equivalent NAND gate, and circuit area that have a great influence

Active Publication Date: 2019-09-24
UNIV OF SCI & TECH OF CHINA
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Problems solved by technology

[0003] The only nonlinear computing unit in SM4 is the S-box, which is used in key expansion and round functions, so it has a great impact on the circuit area of ​​the entire SM4 algorithm. How to reduce the circuit area of ​​the S-box is particularly important. Some related optimization methods use the isomorphic mapping method based on the compound fiel

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  • Method and device for realizing S box in SM4 algorithm
  • Method and device for realizing S box in SM4 algorithm
  • Method and device for realizing S box in SM4 algorithm

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[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0051] The S-box is the only non-linear computing unit in the SM4 algorithm. It is generally realized by using a lookup table. Table 1 shows its visual representation. The first nibble of the input is the row number, and the second nibble is the column. number, the data at the intersection of rows and columns is the output of the S box, assuming the input is 'ef', the row number is e and the column number is f, and the value after nonlinear transf...

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Abstract

The invention provides a method for realizing an S box in an SM4 algorithm, which comprises the following steps: performing first affine transformation and isomorphic transformation on an input element of the S box in a finite field GF (28) to obtain an element in a composite field; decomposing the inverse multiplication operation of the element in the composite domain into inverse operation and multiplication operation on GF (24), performing inverse operation on GF (24) on a polynomial ring base, and performing multiplication operation on GF (24) on a redundant representation base to obtain an inverse element on the composite domain; and performing inverse isomorphic transformation and second affine transformation on the inverse element in the composite domain to obtain an output result of the S box. Calculation of the S box is carried out on the basis of corresponding high efficiency, so that the structure of the S box is more compact and efficient, and the circuit area and time delay of the S box in the SM4 algorithm are further reduced.

Description

technical field [0001] The present invention relates to the technical field of cryptographic algorithm hardware implementation, and more specifically, to a method and device for implementing an S-box in an SM4 algorithm. Background technique [0002] SM4 is a block cipher algorithm used by wireless LAN products. It was approved by the State Cryptography Administration in 2006 and is the first commercial cipher algorithm officially announced in China. With the development of the standardization of cryptographic algorithms in my country, the SM4 algorithm was released in March 2012 as the national cryptographic industry standard. It was released as a national standard in August 2016. [0003] The only nonlinear computing unit in SM4 is the S-box, which is used in key expansion and round functions, so it has a great impact on the circuit area of ​​the entire SM4 algorithm. How to reduce the circuit area of ​​the S-box is particularly important. Some related optimization metho...

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Application Information

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IPC IPC(8): H04L9/06
CPCH04L9/0618H04L2209/122H04L2209/80
Inventor 胡红钢陈颖
Owner UNIV OF SCI & TECH OF CHINA
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