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Module controller for memory device and memory module including module controller

一种存储器、存储单元的技术,应用在静态存储器、仪器、检测有故障的计算机硬件等方向,能够解决故障存储单元概率增大等问题

Active Publication Date: 2019-10-29
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the number of memory cells in a semiconductor memory device increases, the probability of forming a defective memory cell may also increase

Method used

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  • Module controller for memory device and memory module including module controller
  • Module controller for memory device and memory module including module controller
  • Module controller for memory device and memory module including module controller

Examples

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Embodiment Construction

[0029] In the following description of the embodiments, it will be understood that the terms "first" and "second" are intended to identify elements, but are not used to merely limit the elements themselves or mean a specific sequence. In addition, when an element is referred to as being “on,” “over,” “above,” “below,” or “under” another element, it is intended to mean a relative positional relationship, and is not used to limit some of the following Situation: That is, the element directly contacts the other element, or at least one intervening element exists therebetween. Accordingly, terms such as "above," "above," "above," "below," "below," "beneath," etc., are used herein for the purpose of describing particular embodiments only, and No limitation of the scope of the present disclosure is intended. Also, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly electrically or mechanically connected or coupled to the ...

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Abstract

The application provides a module controller for a memory device and a memory module including the module controller. A test circuit includes a built-in self-test (BIST) circuit and a built-in repairanalysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. The built-in repair analysis (BIRA) circuit receives the fail information from the BIST circuit to select at least one of the plurality of memory packages as a repair target memory package. The repair target memory package is selected by considering an error correction capability of an error correction code (ECC) circuit and usability of redundancy regions included in each of the plurality of memory packages.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to Korean Application No. 10-2018-0045080 filed on April 18, 2018, which is incorporated herein by reference in its entirety. technical field [0003] Various embodiments of the present disclosure relate to memory devices, and more particularly, to module controllers for memory devices and memory modules including the same. Background technique [0004] As semiconductor memory devices have become more highly integrated, the storage capacity of semiconductor memory devices has rapidly increased with the development of semiconductor technology. An increase in the memory capacity of semiconductor memory devices may result in an increase in the number of memory cells included in each semiconductor memory device. If the number of memory cells in a semiconductor memory device increases, the probability of forming a defective memory cell may also increase. Thus, the cell array region of each...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/12G11C29/42
CPCG11C29/12G11C29/42G11C29/4401G11C5/04G06F11/1048G06F11/27G11C29/52G06F11/1068
Inventor 禹洙海
Owner SK HYNIX INC