A Sensitivity Analysis Method for Comparing Circuit Sweep Simulation Increments

Abstract

A sensitivity analysis method for comparing circuit scanning simulation increments, comprising the following steps: constructing an IC circuit timing path set and a discrete set of scanning simulation condition factors, obtaining a scanning simulation parameter set of the circuit timing path through SPICE simulation; processing the scanning simulation data , calculate the incremental relative difference percentage, eliminate the difference between the dimension of the timing simulation parameter and its data distribution; calculate the sensitivity factor according to the incremental relative difference percentage; use the obtained scanning simulation condition factor and the incremental value of the simulation parameter Perform visual analysis of relative difference percentage data; calculate comprehensive sensitivity factor index. The present invention also provides a sensitivity analysis system for comparing circuit scan simulation increments, which performs sensitivity analysis on the simulation timing results of SPICE scanning of the target circuit, so that the final calculated sensitivity factor can be better compared between multiple types of timing simulation parameters. The comparison makes the sensitivity analysis of the scanning simulation process simple and intuitive.

Description

Technical field [0001] The present invention relates to the field of EDA design, particularly to a sensitivity analysis method comparing the increments of circuit sweep simulation. Background [0002] In the process of application-specific Integrated Circuit logic design and physical design of application-specific integrated circuits, designers must strictly consider timing constraints (from the establishment and verification of timing to the confirmation of final timing). With the development of IC manufacturing processes, especially after entering the deep submicron process conditions, the traditional and commonly used static timing analysis STA (Static Timing Analysis) method cannot completely contain various factors affecting the delay calculation, cannot verify circuit function, cannot be applied to multiple types of circuits, and is expensive (new process library construction and tool support). At this point, engineers will turn to the Dynamic TimingAnalysis method, which i...

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Problems solved by technology

However, the latter method requires a large number of test vectors in order to improve the coverage of timing critical paths, including multiple reference factors such as operating voltage, temperature, process, input excitation, load, etc., and when the IC design scale increases, its resource consumption and Time consumption will also increase significantly

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