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Method for forming semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve problems such as high cost, and achieve the effect of reducing accuracy requirements, increasing distance, and reducing costs

Active Publication Date: 2022-02-15
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the gradual reduction in the size of semiconductor devices, the distance between adjacent lead-out structures is also getting smaller and smaller. Therefore, it is necessary to use a high-precision photolithography machine to etch, which requires a higher cost.

Method used

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  • Method for forming semiconductor device
  • Method for forming semiconductor device
  • Method for forming semiconductor device

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Embodiment Construction

[0023] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0024] refer to figure 1 , the invention provides a method for forming a semiconductor device, comprising:

[0025] S11: providing a substrate;

[0026] S12: sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on the substrate;

[0027] S13: sequentially etch the control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer to expose the surface of the substrate to form a plurality of square arrays an...

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Abstract

The invention provides a method for forming a semiconductor device, comprising: providing a substrate; sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on the substrate; sequentially etching the control gate layer , the second dielectric layer, the floating gate layer and the first dielectric layer expose the surface of the substrate to form a plurality of square arrays and a plurality of lead-out structures, each of the square arrays has a plurality of said Lead-out structure; a multi-column gate structure gate structure is formed on the square array to form a storage unit, the gate structure has two ends, one end of each column gate structure has a lead-out structure, adjacent column gates The lead-out structures of the pole structures are located at different ends. After the memory cells are formed, the lead-out structures are located at different ends of adjacent columns, which increases the distance between adjacent lead-out structures. Therefore, during etching, the requirements for the accuracy of the lithography machine are reduced, and lower-precision lithography can be used. machine, thus reducing costs.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor device. Background technique [0002] The gate structure can be used as a storage unit. Multiple storage units can form a storage unit. The storage unit is divided into multiple rows and multiple columns of gate structures. The control gates of the storage units located in the same column are connected to a line through the lead-out structure , you can control the storage unit of this column through this line. In the prior art, before forming the gate structure, etching forms a plurality of lead-out structures, and then etches to form the gate structure. The plurality of gate structures form a storage unit, and the storage unit is divided into multiple columns of gate structures. With one lead-out structure, multiple lead-out structures are located at the same end of each column. In the prior art, the method for forming the lead-out s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11521
CPCH10B41/30
Inventor 高超
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP