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A data buffer and data processing method

A data buffer and data processing technology, applied in the direction of electrical digital data processing, data conversion, instruments, etc., can solve the problems of lack of flexibility, complex data storage logic, etc., and achieve the effect of simple control logic and hardware design

Active Publication Date: 2020-11-06
中昊芯英(杭州)科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this implementation, the logic of data storage is complex and lacks flexibility

Method used

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  • A data buffer and data processing method
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  • A data buffer and data processing method

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Embodiment Construction

[0065] The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention.

[0066] It should be understood that the terms "first", "second", "third" and "fourth" in the specification, claims and drawings of this application are used to distinguish different objects, rather than to describe specific objects. order. Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

[0067] Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connectio...

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PUM

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Abstract

The embodiment of the invention discloses a data buffer and a data processing method, the method is applied to the data buffer, the data buffer comprises a controller and a first register, and the method comprises the following steps: when the data buffer is in a writing state, the data buffer sends N rows of shift control signals to the storage space of the first register through the controller,wherein the N rows of shift control signals move for a preset unit length in each preset unit time according to a first preset direction, the N rows of shift control signals are used for instruct thestorage space of the first register to store the input matrix data according to a second preset direction; the data buffer stores input matrix data through the first register according to the N rows of shift control signals. By implementing the method, the ordered controllability of the complex storage process is realized by matching simple hardware design with the shift control signal.

Description

technical field [0001] The invention relates to the technical field of computer storage, in particular to a data buffer and a data processing method. Background technique [0002] At present, in the current ASIC (Application Specific Integrated Circuit, ASIC) design, the data buffer is usually set by setting an appropriate number of first-in-first-out queue (First Input First Output, FIFO) data buffers to prevent data loss. Or handle data failures. Specifically, the FIFO data buffer implements a first-in-first-out policy during the data dumping process, for example, the data that enters first is read out from the FIFO data buffer first. [0003] In the prior art, the working principle of FIFO can be described as: using independent read and write pointers to sequentially write data into storage units under the control of read and write pulses, or to sequentially read data from storage units. Taking data storage as an example, the data is stored in the position of the write ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F5/06G06F5/08
CPCG06F5/065G06F5/08
Inventor 郑瀚寻闯小明杨龚轶凡张斌
Owner 中昊芯英(杭州)科技有限公司