Control circuit for ternary content addressable memory

Abstract

The invention discloses a control circuit for a ternary content addressable memory. The control circuit for a ternary content addressable memory comprises a first logic unit and a second logic unit, wherein the first logic unit is coupled to the first storage unit, the second storage unit, the first lookup line, the second lookup line, the reference voltage end and the matching line; the second logic unit is coupled to the first storage unit, the second storage unit, the first lookup line, the second lookup line, the first power supply line and the second power supply line; and when the voltage of the first lookup line and the voltage of the second lookup line are matched with the voltage of the first storage unit and the voltage of the second storage unit, the second logic unit provides apath to enable the first power supply line to be electrically connected with the second power supply line.

Description

technical field [0001] The invention relates to a control circuit of a three-state content addressing memory, in particular to a control circuit electrically connected to two power supply lines when the voltages of the search line and the storage voltage match each other. Background technique [0002] A ternary content-addressable memory (TCAM for short) is commonly used in applications supporting a large number of searches because it can support high-speed searches, such as searching for URLs. In a common 3-state content addressable memory, each memory cell can support data in three states: 1, 0 and don't care. Since multiple storage units can be set in array form, when a large number of searches are performed, multiple storage units can be compared synchronously, so high-speed search can be supported. However, this architecture has technical disadvantages as follows. In the known architecture, multiple memory cells are coupled to the match line together, and the match li...

AI Technical Summary

Problems solved by technology

However, when the number of memory cells coupled to the match line is large, it is difficult to avoid unexpected leakage due to the increased load

Therefore, it may happen that the data of all memory cells has been matched, but the voltage of the matching line is mistakenly dropped too low due to leakage, resulting in subsequent misjudgment

In addition, the node voltage on the match line may also falsely drop due to the effect of charge sharing, resulting in misjudgment

[0003] In addition to the lack of the above two items that may cause misjudgment, the current 3-state content addressable memory must first charge the matching line during the pre-charging period, and then observe the voltage change of the matching line during the evaluation period, resulting in increased operational temporal complexity. It also makes the design more difficult

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