Semiconductor layout and layout method thereof
A semiconductor and layout technology, applied in special data processing applications, instruments, electrical and digital data processing, etc., can solve the problems of difficult coordination and matching of layer relationships, affecting circuit digital or analog devices, etc., to achieve reliable semiconductor layout and avoid parasitic effects. Effect
Pending Publication Date: 2020-02-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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[0004] However, when using the above scheme to deal with the insertion of graphics at multiple levels, the relationship between the filled layers is difficult to coordinate and match. Once the layers overlap each other, it is easy to generate parasitic effects such as parasitic transistors and parasitic capacitance resistances, which affect the circuit. other digital or analog devices
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[0043] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.
[0044] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...
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The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor layout and a layout method thereof. The semiconductor layout comprises a predetermined region and a filling region; wherein the predetermined region comprises an active layer and / or a gate layer; wherein the filling region comprises at least one filling pattern, the filling pattern comprises a filling active layer and a filling gate layer, and the pattern of the filling pattern is generated according to the pattern density of the active layer and the gate layer of the predetermined region. The layout method of the semiconductor layout comprises the following steps: acquiring pattern densities of an active layer and a gate layer in a predetermined region; generating a filling pattern according to the pattern density of the active layer and the gate layer in the predetermined region; and filling the filling region in the predetermined region with the filling pattern to generate the semiconductor layout. According to the invention, the filling area is integrally filled with the filling pattern, so that the problem of relationship coordination and matching between the active layer and the gate layer in the pattern filling process is avoided.
Description
technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor layout and a layout method of the semiconductor layout. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the integration level of semiconductor devices has also been continuously improved. In the semiconductor manufacturing process, chemical mechanical polishing (Chemical Mechanical Polishing, CMP) is a process for realizing the planarization of the surface of semiconductor devices. In order to meet the requirements of the CMP process, it is usually required "Filled area") to insert a filled shape. [0003] Related technologies usually adopt a solution to optimize the insertion of a single-level filling pattern. For example, when inserting an active layer and a gate layer in a semiconductor layout, a single insertion will only insert an active layer pattern or a gate layer ...
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Inventor 李彦正
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP