Memory access instruction processing method and processor

Abstract

The embodiment of the invention provides a memory access instruction processing method and a processor. The method comprises the steps: reading a memory access instruction from a cache, and obtainingthe criticality of the memory access instruction from the cache, wherein the criticality of the memory access instruction is in a positive correlation relationship with assembly line dwell time causedby the memory access instruction, and the criticality of the memory access instruction is stored in an instruction cache block of the cache; when the memory access instruction is executed, adjustingthe execution priority of the memory access instruction according to the criticality of the memory access instruction, wherein the criticality of the memory access instruction is in positive correlation with the execution priority of the memory access instruction; outputting an execution result corresponding to the memory access instruction; and executing memory access according to the execution result. According to the embodiment of the invention, the pipeline pause time caused by memory access delay can be reduced, and the processing efficiency of the processor is improved.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of processors, and in particular to a memory access instruction processing method and a processor. Background technique [0002] Modern processors generally use pipeline technology to process instructions in parallel to speed up instruction processing efficiency; instructions processed by processors include but are not limited to: branch instructions, logical operation instructions, memory access instructions, etc.; where memory access instructions refer to instructions for accessing storage . [0003] In the process of processing memory access instructions, memory access latency is one of the reasons that affect processor performance; if the processor executes subsequent instructions that depend on the memory access results of memory access instructions, it takes a long time to access storage to obtain memory access results (That is, the memory access delay is relatively large), which...

AI Technical Summary

Problems solved by technology

[0003] In the process of processing memory access instructions, memory access latency is one of the reasons that affect processor performance; if the processor executes subsequent instructions that depend on the memory access results of memory access instructions, it takes a long time to access storage to obtain memory access results (That is, the memory access delay is relatively large), which will cause the pipeline to pause for a long time, which will cause the performance loss of the processor; it can be seen that the memory access delay is a common cause of the long-term pause of the pipeline, so it is urgent to provide a method for accessing New processing method of store instruction to reduce memory access delay

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