Method for improving morphology of capacitor holes

Abstract

The invention provides a method for improving the morphology of a capacitor hole, and the method at least comprises the following steps: providing a semiconductor substrate, and sequentially depositing an etching stop layer, at least one capacitor sacrificial oxide layer, a first capacitor supporting layer and a third capacitor sacrificial oxide layer on the semiconductor substrate; and etching the third capacitor sacrificial oxide layer until the first capacitor support layer stops, and forming a capacitor hole upper opening in the third capacitor sacrificial oxide layer. The width of the upper opening of the capacitor hole is greater than that of the required capacitor hole, and a barrier layer is deposited on the side wall and the top of the upper opening of the capacitor hole to realize miniaturization of the opening, thereby reducing the photoetching difficulty; the barrier layer can protect the side wall of the capacitor hole, so that the top morphology of the capacitor opening is kept relatively good, the inclination is relatively small, and the possibility of bridging at the top is greatly reduced. Nitride is filled after the capacitor hole is etched to form the supportinglayer at the top of the capacitor hole, so that the etching difficulty of the capacitor hole is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for improving the morphology of capacitor holes. Background technique [0002] With the development of semiconductor technology, dynamic random access memory (DRAM) devices are getting smaller and smaller, the aspect ratio of capacitors is getting bigger and bigger, etching is becoming more and more difficult, and the shape control of capacitor holes is becoming more and more difficult. more difficult. [0003] Such as Figure 1-3 As shown, the method for forming capacitor holes in the prior art is shown. Such as figure 1 As shown, an etch stop layer 201, a first capacitor sacrificial oxide layer 202, a second capacitor sacrificial oxide layer 203, a first capacitor supporting layer 204, a third capacitor sacrificial oxide layer 205, and a second capacitor oxide layer 201 are sequentially deposited on a substrate 101. A supporti...

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