Integrated circuit and clock and data recovery circuit including the integrated circuit

Abstract

An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least onephase-shifted clock signal.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of Korean Patent Application No. 10-2018-0122043 filed with the Korean Intellectual Property Office on October 12, 2018, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0003] Exemplary embodiments of the inventive concept relate to integrated circuits and clock and data recovery circuits, and more particularly, to detecting a target frequency in a short time by simultaneously and conveniently tracking phase and frequency errors between an input data signal and a clock signal An integrated circuit, or a clock and data recovery circuit comprising such an integrated circuit. Background technique [0004] A conventional clock and data recovery (CDR) technique divides input data to generate a fixed reference clock signal, and operates a frequency locked loop by using the fixed reference clock signal to find a target frequency. Until now, fr...

AI Technical Summary

Problems solved by technology

In this traditional CDR technology, in the process of frequency division from the input data, the incorrect reference clock signal is determined as the final fixed frequency through the frequency locked loop, and due to the characteristics of the frequency division method, the reference clock signal is slows down, so there is a disadvantage that it takes a lot of time until the frequency is fixed

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