Method and system for quickly verifying IP prototype of FPGA platform

Abstract

The invention discloses a rapid verification method and system for an IP prototype of an FPGA platform, and the method comprises the steps: providing a stable system environment through employing a platform-oriented idea to avoid the repeated development of a plurality of systems. As a plurality of IPs shares a system platform, the repeated debugging of JTAG, a bus and UART is avoided to save theearly workload. As the independent comprehensive part of the IPs is small in logic quantity, the comprehensive and layout wiring speed is high, a designer can conveniently adjust and design in time,and the IP development time is saved; system design and IP debugging are separated, IP developers can focus on IP debugging conveniently, and task allocation is facilitated. For the development of theplurality of IPs, the main difference is reflected in an IP lower part, and the reusability is strong.

Description

technical field [0001] The invention relates to the technical field of ASIC / SOC chip design, and more specifically relates to a method and system for fast verification of an FPGA platform IP prototype. Background technique [0002] At present, as chip design enters the SOC (System on Chip) stage, IP prototype verification has become an important work of design, and FPGA prototype verification is currently the mainstream technical means. Under the traditional FPGA platform, first prepare each IP that needs to be verified, and then complete the integration, then perform comprehensive layout and wiring, generate a bit file, and finally download it to the FPGA platform, and the developer performs the system and each IP to be verified one by one Validation and debugging. The specific traditional FPGA platform IP prototype verification architecture is attached figure 1 shown. attached by figure 1 It can be seen that the IP verification process under the traditional FPGA protot...

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Problems solved by technology

[0014] In view of this, the present invention provides a method and system for rapid verification of an FPGA platform IP prototype. The method separates the debugging upper part and the IP lower part into two separate parts, which are respectively integrated into independent bit files, system design and IP debugging. Separated to solve the problems of low efficiency, difficult debugging and high error rate caused by repeated development of multiple systems

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