Method and system for quickly verifying IP prototype of FPGA platform
A verification method and verification system technology, applied in FPGA platform IP prototype rapid verification method and system field, can solve problems such as low efficiency, difficult debugging, high error rate, etc., achieve less logic, save early work, and reusability strong effect
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[0040] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0041] On the one hand, see appendix figure 2 , an embodiment of the present invention discloses a rapid verification method for an IP prototype of an FPGA platform, the method comprising the following steps:
[0042] S1: Separate the debugging upper part and the IP lower part, and synthesize them into independent bit files;
[0043] S2: According to the IP development rate, a corresponding type of master-slave interface is set betw...
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