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Chip testing system and method

A technology for chip testing and chips to be tested, applied in fault hardware testing methods, error detection/correction, detection of faulty computer hardware, etc., can solve problems such as re-transplantation, and achieve the effect of simultaneous testing and verification

Pending Publication Date: 2020-05-05
小华半导体有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the limitation of this method is that if there is an increase in test items, it is necessary to modify the programs on both sides of the relevant test equipment and inside the chip at the same time.
And if the follow-up does not use a Windows system PC, but other professional test equipment for testing, it is necessary to re-transplant the relevant test program

Method used

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  • Chip testing system and method
  • Chip testing system and method
  • Chip testing system and method

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Embodiment Construction

[0040] In the following description, the present invention is described with reference to various examples. One skilled in the art will recognize, however, that the various embodiments may be practiced without one or more of the specific details, or with other alternative and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive concepts of the present invention. Similarly, for purposes of explanation, specific quantities, materials and configurations are set forth in order to provide a thorough understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to correct scale.

[0041] In this specification, reference to "one embodiment" or "the embodiment...

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Abstract

The invention discloses a chip testing system. The chip testing system comprises a testing terminal and N to-be-tested chips of the same type or different types, wherein the N to-be-tested chips are connected with the testing terminal through a bus. The to-be-tested chips adopt a Modbus communication protocol to realize data interaction with a test terminal, and meanwhile, data formats in the system are all defined by Protol buffers.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to chip verification and testing technology. Background technique [0002] With the continuous development of chip technology, chip functions are becoming more and more complex. In order to ensure the reliability of the chip, functional verification and testing are required after the chip design is completed. [0003] Usually, each function of each module of the chip needs to have independent test items, so for chips with high internal IP complexity, the number of test items is large, and at the same time, small batch chips need to be independently verified for each chip test. When a chip tester changes a test item or parameter, since a new test program needs to be re-downloaded in each chip, once the test item changes, the chip test will consume a lot of manpower. [0004] In response to this phenomenon, the current common practice is to use the test program to add multipl...

Claims

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Application Information

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IPC IPC(8): G06F11/22
CPCG06F11/2273G06F11/2268
Inventor 庞伟
Owner 小华半导体有限公司