Processor compatible with multi-instruction system and operation method thereof

Abstract

The invention provides a processor compatible with a multi-instruction system and an operation method of the processor, and the processor comprises: a programmable decoding part which is used for decoding a to-be-executed instruction into a micro-operation code according to a pre-programmed instruction system; an execution component which is used for executing the microoperation code by reading and writing the data cache to obtain an execution result; and a write-back and submission component whch is used for writing back and submitting the execution result and then ending the execution of theinstruction. According to the invention, the same processor can be efficiently compatible with various different instruction systems with low hardware cost.

Description

technical field [0001] The invention relates to the field of processor (CPU) design, and in particular to a processor compatible with a multi-instruction system and an operating method thereof. Background technique [0002] Existing processors are all hardware implementations, usually using a pipelined structure, such as figure 1 As shown, it includes the main components such as fetching, decoding, register renaming, dispatching, launching, executing, writing back, and submitting. Among them, the instruction fetching unit reads instructions from the instruction cache, and after decoding and register renaming, it forms micro-ops that can be executed by subsequent components. The instruction micro-operations after the code and register renaming are stored in the launch queue to wait for launch; launch is to select the instruction micro-operations that meet the execution conditions from the launch queue to the execution unit for execution. The dispatch unit and the issue unit...

AI Technical Summary

Problems solved by technology

However, the same processor cannot be compatible with different instruction systems in hardware. For example, the X86 processor cannot execute the MIPS instruction system or the ARM instruction system in hardware, and vice versa.

Compatibility with different instruction systems can only be achieved in the form of software binary translation, which is achieved by running virtual machine software that simulates other instruction systems on the native processor, which is very inefficient

Images