Processor compatible with multi-instruction system and operation method thereof

A technology of instruction system and operation method, applied in concurrent instruction execution, machine execution device, electrical digital data processing, etc., can solve the problem of low efficiency, X86 processor cannot hardware execute MIPS instruction system, processor cannot hardware compatible instruction system, etc. problem, to achieve the effect of maintaining execution efficiency and small hardware cost

Active Publication Date: 2020-05-08
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the same processor cannot be compatible with different instruction systems in hardware. For example, the X86 processor cannot execute the MIPS instruction system or the ARM instruction system in hardware, and vice versa.
Compatibility with different instruction systems can only be achieved in the form of software binary translation, which is achieved by running virtual machine software that simulates other instruction systems on the native processor, which is very inefficient

Method used

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  • Processor compatible with multi-instruction system and operation method thereof
  • Processor compatible with multi-instruction system and operation method thereof
  • Processor compatible with multi-instruction system and operation method thereof

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Embodiment Construction

[0039] The microstructures and functions of existing processors with different instruction systems are very similar. Such as figure 1 As shown, all adopt the pipeline structure, and the functions of each part of the pipeline are similar, and the biggest difference is the decoding part. The decoding components of different processors implement instruction decoding of different instruction systems, which are different from each other. Since the decoding component is implemented by hardware and cannot be changed dynamically, this results in a processor that implements a specified instruction system not being compatible with other instruction systems in hardware. However, if the decoding component is implemented in a software programmable manner, then only the decoding software of the software decoding component is updated to switch to another instruction system processor without affecting the execution efficiency of the processor at all.

[0040] The present invention includes ...

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Abstract

The invention provides a processor compatible with a multi-instruction system and an operation method of the processor, and the processor comprises: a programmable decoding part which is used for decoding a to-be-executed instruction into a micro-operation code according to a pre-programmed instruction system; an execution component which is used for executing the microoperation code by reading and writing the data cache to obtain an execution result; and a write-back and submission component whch is used for writing back and submitting the execution result and then ending the execution of theinstruction. According to the invention, the same processor can be efficiently compatible with various different instruction systems with low hardware cost.

Description

technical field [0001] The invention relates to the field of processor (CPU) design, and in particular to a processor compatible with a multi-instruction system and an operating method thereof. Background technique [0002] Existing processors are all hardware implementations, usually using a pipelined structure, such as figure 1 As shown, it includes the main components such as fetching, decoding, register renaming, dispatching, launching, executing, writing back, and submitting. Among them, the instruction fetching unit reads instructions from the instruction cache, and after decoding and register renaming, it forms micro-ops that can be executed by subsequent components. The instruction micro-operations after the code and register renaming are stored in the launch queue to wait for launch; launch is to select the instruction micro-operations that meet the execution conditions from the launch queue to the execution unit for execution. The dispatch unit and the issue unit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/383G06F9/384G06F9/3869
Inventor 王剑
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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