Handling effective address synonyms in a load-store unit that operates without address translation

Abstract

Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of- order (OoO) window. The issuing includes, in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address. Further, the execution includes in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry, and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.

Description

technical field [0001] Embodiments of the present invention relate generally to out-of-order (OoO) processors, and more specifically to utilizing a synonym detection table (SDT) to handle effective address synonyms in load-store units that operate without address translation. Background technique [0002] In an OoO processor, the instruction sequencing unit (ISU) dispatches instructions to each issue queue, renames registers that support OoO execution, issues instructions from each issue queue to the execution pipeline, completes executed instructions, and handles exception conditions . Register renaming is typically performed by the mapper logic in the ISU before instructions are placed in their respective issue queues. The ISU includes one or more issue queues that contain dependency matrices for tracking dependencies between instructions. A dependency matrix typically includes a row and a column for each instruction in the issue queue. [0003] In the domain of central...

AI Technical Summary

Problems solved by technology

When two or more instructions require part of the processor's hardware at the same time, such as when accessing a memory location both in the fetch phase of retrieving an instruction from memory and in the store phase of writing data and / or reading data from memory , a structural hazard occurs

Also, branch hazards (also known as control hazards) occur with branches in computer programs executed by processors

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