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Detection method and device for integrated circuit layout, design method and electronic equipment

A technology of integrated circuits and detection methods, which is applied in computer-aided design, calculation, electrical digital data processing, etc., can solve the problems of missing or missing vias between metal layers of integrated circuit layouts, so as to avoid chip dysfunction and avoid The effect of increased resistance

Active Publication Date: 2020-05-15
SHANGHAI AISINOCHIP ELECTRONICS TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The present invention provides a detection method, device, design method and electronic equipment of an integrated circuit layout to solve the problem of being unable to detect whether there is an omission or absence of a via hole between metal layers in the integrated circuit layout

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  • Detection method and device for integrated circuit layout, design method and electronic equipment
  • Detection method and device for integrated circuit layout, design method and electronic equipment
  • Detection method and device for integrated circuit layout, design method and electronic equipment

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Embodiment Construction

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0042] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above drawings are used to distinguish similar objects and not necessarily Describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or...

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Abstract

The invention provides an integrated circuit layout detection method and device, a design method and electronic equipment, and the method comprises the steps: determining a GDS file of a to-be-detected current metal network; obtaining a metal wire coordinate of each metal wire from the GDS file; obtaining coordinates of an existing via hole from the GDS file; and determining the coordinates of theomitting via hole and / or the missing via hole according to the coordinates of the metal wire and the coordinates of the existing via hole. According to the invention, metal wire resistance increase caused by via hole omission or missing can be effectively avoided, so that the situations of chip function disorder, electromigration, direct burning and the like can be avoided.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a detection method, device, design method and electronic equipment for an integrated circuit layout. Background technique [0002] The layout of an integrated circuit can be understood as a drawing for making a mask, in which the active region layer, polysilicon layer, P selection layer, N selection layer, metal layer, etc., can be connected by via holes the corresponding metal layer. [0003] In the prior art, when detecting the layout of the integrated circuit, it can be detected whether the layout design of the integrated circuit is consistent with the principle circuit Figure 1 Consistency, and whether it is consistent with the design rules of integrated circuits, etc. However, there is no way to detect whether there is omission or absence of vias between metal layers in the layout of the integrated circuit. Contents of the invention [0004] The invention provides a d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398
Inventor 高敬周玉洁孙坚
Owner SHANGHAI AISINOCHIP ELECTRONICS TECH