Method and system for relieving write interference of phase change memory

A technology of phase change memory and write interference, which is applied in static memory, digital memory information, information storage, etc., can solve the problems of high performance overhead, etc., and achieve the effect of alleviating write interference errors, alleviating write interference, and avoiding performance loss

Active Publication Date: 2020-05-29
SHANDONG UNIV
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Problems solved by technology

VnC can easily cause cascaded RESET operati

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  • Method and system for relieving write interference of phase change memory
  • Method and system for relieving write interference of phase change memory
  • Method and system for relieving write interference of phase change memory

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[0028] The present disclosure will be further described below in conjunction with the accompanying drawings and embodiments.

[0029] It should be noted that the following detailed description is exemplary and intended to provide further explanation of the present disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0030]It should be noted that the terminology used herein is only for describing specific embodiments, and is not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural, and it should also be understood that when the terms "comprising" and / or "comprising" are used in this specification, they mean There are features, steps, operations, means, components and / or combinations thereof.

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Abstract

The invention provides a method and system for relieving write interference of a phase change memory, and the method comprises the steps: dynamically searching an idle main memory block at a bit linelevel, so as to determine a writable reliable idle main memory block, and achieve the dynamic sensing; and at the word line level, comparing the new data with expected data, detecting whether a writeinterference error occurs or not, and if the write interference error occurs, performing correction operation. The performance and overhead of the PCM memory are balanced to a certain extent, the occurrence of PCM write interference errors is effectively relieved, the reliability of data storage is ensured, the performance loss caused by cascading is fundamentally avoided, and the overall performance loss of the PCM is reduced.

Description

technical field [0001] The disclosure belongs to the technical field of non-volatile memory, and relates to a method and system for alleviating write interference of a phase-change memory. Background technique [0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art. [0003] With the advent of the era of big data, the demand for memory performance has also increased. Building a main memory system with high access bandwidth, high scalability, and high density has become a major challenge for modern computing systems. However, traditional DRAM memory loses data when it is powered off, and its density and scalability have faced development bottlenecks. These shortcomings limit the performance improvement of DRAM, making it unable to keep up with the pace of big data storage. Research in recent years has found that Phase Change Memory (PCM), as an emerging non-volatile memory, h...

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Application Information

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IPC IPC(8): G11C13/00
CPCG11C13/0004G11C13/0033
Inventor 蔡晓军靳文科蔡文浩陆思奇张志宇刘忠洋
Owner SHANDONG UNIV
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