Pipeline control method and related equipment
A control method and assembly line technology, applied in the direction of program control design, instrumentation, calculation, etc., can solve problems such as increased processing burden and complicated detection process
Active Publication Date: 2020-11-20
上海燧原智能科技有限公司
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Problems solved by technology
[0004] This makes the detection process of data hazards very complicated and increases the processing load of the CPU.
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[0047] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0048] Such as figure 1 As shown, a pipeline control method provided by an embodiment of the present invention may include:
[0049] S001. Determine a target instruction to be sent in a current clock cycle.
[0050] Among them, there may be multiple types of target instructions, such as unconditional write instructions, conditional write instructions, read instructions, and so on. According to different instruction types, the pre...
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The invention discloses an assembly line control method and related equipment. The method comprises the following steps: determining a target instruction to be sent in a current clock period; when conditions and operands are needed when the target instruction is executed, determining a condition request level difference of the conditions needed when the target instruction is executed, and determining an operand request level difference of the operands needed when the target instruction is executed; determining a first target condition register resource where a condition required by the targetinstruction is located, determining whether the condition request level difference is not less than a condition maximum level difference of the first target condition register resource in a current clock period, and obtaining a first judgment result; determining a first target data register resource where an operand required by the target instruction is located, determining whether an operand request level difference is not less than an operand maximum level difference of the first target data register resource in a current clock period, and obtaining a second judgment result; and when both the first judgment result and the second judgment result are yes, sending a target instruction in the current clock period. According to the invention, the burden of the CPU is reduced.
Description
technical field [0001] The invention relates to the field of processor performance optimization, in particular to a pipeline control method and related equipment. Background technique [0002] Pipeline technology refers to a quasi-parallel processing implementation technology in which multiple instructions overlap and operate during program execution. But pipeline technology also has the problem of data risk. [0003] Existing central instruction scoreboard algorithms for sequentially executing CPUs maintain information about all executing instructions among sequentially executing CPUs. Before issuing each new instruction, the algorithm checks the current instruction and all executing instructions for resource conflicts. If N instructions are issued per clock cycle, and the longest pipeline depth (representing the maximum number of outstanding instructions) is L, then the number of resource conflicts that the algorithm needs to check is N*L*N. [0004] This makes the dete...
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IPC IPC(8): G06F9/38
CPCG06F9/3869
Inventor 冯闯
Owner 上海燧原智能科技有限公司