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Sequence cyclic shift device and method and storage medium

A technology of a shift device and a shift register, which is applied in the direction of error detection coding, coding, and code conversion using multi-bit parity bits.

Active Publication Date: 2020-06-09
SPREADTRUM SEMICON (NANJING) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem solved by the present invention is how to support the shift operation of a longer sequence while reducing the complexity of the cyclic shift device

Method used

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  • Sequence cyclic shift device and method and storage medium
  • Sequence cyclic shift device and method and storage medium
  • Sequence cyclic shift device and method and storage medium

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Embodiment Construction

[0032] As mentioned in the background art, the existing QSN network, Banyan network, and Benes network cannot support long-sequence shift operations.

[0033] among them, figure 1 It is a schematic diagram of the structure of the QSN network in the prior art, refer to figure 1 , QSN network contains (log 2 (PM)+1) level and each bit width contains (PM·(2·log 2 (PM)-1)+1) "2-1 Multiplexer (MUX)", which can support sequence shift of any input width and any shift scale. figure 2 It is the structural diagram of Banyan network, reference figure 2 , Its switch network contains (log 2 (PM)) level and per bit width PM·log 2 (PM) A "2-1MUX", which can support a sequence shift of input width and arbitrary shift scale. image 3 It is a schematic diagram of the Benes network. reference image 3 , The Benes network contains (2·log 2 (PM)-1) level and width per bit (PM·(2·log 2 (PM)-1)) "2-1MUX", which can support sequence shift of any input width and any shift scale.

[0034] It can be seen th...

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PUM

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Abstract

The invention discloses a sequence cyclic shift device and method and a storage medium. The device comprises: a first set of cyclic shift registers comprising a plurality of first cyclic shifters, a second set of cyclic shift registers comprising a plurality of second cyclic shifters, wherein each output end of the kth first cyclic shifter is sequentially connected to the kth input end of each second cyclic shifter and k is a positive integer, and a sequence rearrangement module suitable for receiving the output data of output ends of the second cyclic shifters and rearranging the sequence ofthe output data to obtain an output sequence, wherein when the sequence with the length of x by v is shifted, the cth first cyclic shifter receives the sub-sequences obtained by splitting the sequenceand shift the sub-sequence, the shift digits are determined according to x, v and c, c is externally input, the shift digits of the dth second cyclic shifter in the length of the sub-sequences are determined according to x, v and c, v, x, c and d are positive integers, and x is smaller than or equal to c*d. According to the scheme of the invention, the shift complexity can be reduced.

Description

Technical field [0001] The present invention relates to the technical field of digital circuits, in particular to a sequence cyclic shift device and method, and a storage medium. Background technique [0002] Currently, the mainstream implementation methods of sequential cyclic shift operations include QuasiCyclic LDPCshift network (QuasiCyclicLDPCshiftnetwork, QSN for short) network, Banyan network, Benes network. When the loop sequence length is small, all three networks can be implemented well. However, since the implementation complexity of the three cyclic shift networks is proportional to the square of the input bit width, when the input sequence length is large, the implementation complexity of the network becomes unacceptable. In actual digital signal algorithms, it is very common to handle large-scale sequence cyclic shift operations, so it is difficult to directly use the above three networks to implement cyclic shift operations with a long sequence length. [0003] How...

Claims

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Application Information

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IPC IPC(8): H03M13/11
CPCH03M13/1148
Inventor 燕威谢静徐志昆
Owner SPREADTRUM SEMICON (NANJING) CO LTD