memory built-in self-test system

Abstract

A built-in self-test system of a memory, comprising: N memory interface modules and N memories coupled one-to-one, and the N memory interface modules are the same, wherein: the i-th memory interface module includes: a self-test controller , a first selector, a second selector, a third selector, a fourth selector, a fifth selector and a self-test result register, the fourth selector is suitable for receiving an external control signal, and according to the external control The signal selects and outputs the data of the first input terminal of the fourth selector or the data of the second input terminal of the fourth selector; the fifth selector is adapted to receive an external control signal, and output according to the external control signal The data of the first input terminal of the fifth selector or the data of the second input terminal of the fifth selector. By adopting the above solution, it is possible to reduce the occupation of the area of ​​the chip by the built-in self-test system of the memory, thereby reducing the area of ​​the chip and reducing the cost of the chip.

Description

technical field [0001] The embodiment of the present invention relates to the technical field of communication, and in particular to a built-in self-test system of a memory. Background technique [0002] At present, in the built-in self-test (MBIST) of the memory, a test-specific logic circuit inside the chip is added during chip design, and the memory inside the chip is tested by using the test-specific logic circuit. LV Flow is an integrated environment for inserting MBIST circuits near the memory of the chip. After adding LV Flow to the specific circuit of the chip, a bypass register for improving the test coverage of combinational logic near the memory needs to be added to the test-specific logic circuit. [0003] However, the number of bypass registers is consistent with the data bit width of the memory, and when more memories are used in the chip, the number of bypass registers is larger, occupying a larger chip area. Contents of the invention [0004] The technical...

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Problems solved by technology

[0003] However, the number of bypass registers is consistent with the data bit width of the memory. When the memory used in the chip is large, the number of bypass registers is large and occupies a large chip area.

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