Tolerance test device and method of semiconductor device
A testing device and semiconductor technology, applied in the direction of single semiconductor device testing, measuring devices, instruments, etc., can solve the problems of high failure rate and limited current rise rate tolerance, and achieve the effect of reducing the failure rate
Active Publication Date: 2020-06-26
JILIN SINO MICROELECTRONICS CO LTD
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[0002] In the application process of high-power semiconductor devices, the inventors of the present application found that due to the limited tolerance of the current rise rate (di / dt), the failure rate is relatively high
Although the traditional methods have relevant protective measures on the application circuit, it is extremely difficult to completely eliminate the phenomenon that the ultra-high current rise rate does not appear in any special case
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[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.
[0052] Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the protection scope of the present application.
[0053] It should be not...
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The embodiment of the invention provides a tolerance test device and method for a semiconductor device. A current impact unit inputs a current impact signal to a to-be-tested semiconductor device according to a set peak current value, a set current rise rate and a set pulse period; a current impact signal on the to-be-tested semiconductor device, the number of test pulses of the current impact signal and the device state of the to-be-tested semiconductor device through the test unit are tested; and a main control unit generates a current rise rate tolerance value of the to-be-tested semiconductor device according to the current impact signal on the to-be-tested semiconductor device, the test pulse frequency of the current impact signal and the device state of the to-be-tested semiconductordevice. Thus, the current rise rate endurance capability of a semiconductor device can be effectively quantified, so that the current rise rate endurance capability of the semiconductor device can beaccurately evaluated subsequently, and the failure ratio of the semiconductor device can be reduced by adopting necessary means.
Description
technical field [0001] The present application relates to the technical field of semiconductor device testing, and in particular, to a semiconductor device endurance test device and method. Background technique [0002] In the application process of high-power semiconductor devices, the inventors of the present application have found that due to the limited tolerance of the current rise rate (di / dt), the failure rate is relatively high. Although the traditional methods have relevant protective measures in the application circuit, it is extremely difficult to completely eliminate the phenomenon that the ultra-high current rise rate does not appear in any special case. Therefore, for a semiconductor device, it is necessary to have an appropriate current rise rate tolerance within a certain range. Based on this, how to effectively quantify the current rise rate tolerance of semiconductor devices, so as to accurately evaluate the current rise rate tolerance of semiconductor dev...
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IPC IPC(8): G01R31/26
CPCG01R31/2601
Inventor 赵建伟姜明宝李强
Owner JILIN SINO MICROELECTRONICS CO LTD