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Impedance calibration circuit and calibration control method for physical interface of computer flash memory device

A computer flash memory and impedance calibration technology, which is applied in the field of integrated circuits, can solve the problems of difficult reduction of power consumption of impedance calibration circuits and low impedance of the drive end, and achieve the effects of improving power consumption performance, reducing system power consumption, and improving process compatibility

Active Publication Date: 2022-05-20
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the strong driving capability required by the ONFi standard in high-speed mode, the impedance of the driving end is low (typically 18-100 ohms), which also makes it difficult to reduce the power consumption of the impedance calibration circuit

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  • Impedance calibration circuit and calibration control method for physical interface of computer flash memory device
  • Impedance calibration circuit and calibration control method for physical interface of computer flash memory device
  • Impedance calibration circuit and calibration control method for physical interface of computer flash memory device

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Embodiment Construction

[0055] The following will clearly and completely describe the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0056] As mentioned in the background, in existing interface circuits, it is difficult to reduce the power consumption of the impedance calibration circuit. In addition, the ONFi standard stipulates that the reference voltage VREF of the DDR interface is 1 / 2 Vccq, but in many advanced technologies, the reference voltage VREF of 1 / 2 Vccq is close to the transistor threshold of the drive circuit, so that the comparison circuit in the impedance calibration circuit is at the ref...

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Abstract

This application discloses an impedance calibration circuit and a calibration control method for a physical interface of a computer flash memory device. In the technical solution of the present invention, the adjustable voltage divider module can divide the output reference voltage into a pull-up reference voltage and a pull-down reference voltage. The adjustable voltage divider module can dynamically adjust the pull-up reference voltage and pull-down reference voltage to improve the power consumption performance of the interface circuit. By combining the driving modules, while having both impedance matching and driving functions, the reasonable configuration of branches with different resistance values ​​can be realized, which can reduce system power consumption and improve process compatibility.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, and more specifically, relates to an impedance calibration circuit and a calibration control method for a physical interface of a computer flash memory device (NAND Flash). Background technique [0002] The NAND physical interface is an important part of the data path in the SSD (solid state disk) or memory card system, and provides a high-speed transceiver drive interface circuit for the data communication link between the NAND and the flash memory controller chip. The transceiver driving circuit of the NAND physical interface usually needs to meet the timing and impedance matching requirements of the international ONFi (Open NAND Flash Interface, open NAND flash memory interface) standard. At present, the latest ONFi standard is ONFi 4.1, which needs to support high-speed interfaces such as NV-DDR (Non-Volatile Double Rate), NV-DDR2 and NV-DDR3, so the timing and impedance matching ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16G06F13/40G11C7/10
CPCG06F13/1668G06F13/4086G11C7/1057G11C7/1084Y02D10/00
Inventor 刘飞陈胜宇霍宗亮
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI