FPGA configuration file arithmetic compression and decompression method based on neural network model

Abstract

The invention discloses an FPGA configuration file arithmetic compression and decompression method based on a neural network model, and the method comprises the steps: defining a content sequence of an FPGA configuration file, and enabling the conditional probability distribution of any symbol under the determination of the first k items of data to serve as the probability of a corresponding symbol in an arithmetic coding process; estimating the probability of each symbol in the FPGA configuration file by using the neural network model; using arithmetic coding and performing arithmetic codingcompression on the probability of each symbol of the predicted FPGA configuration file by using the established neural network; and decompressing the FPGA configuration file. According to the method,the probability estimation of the configuration file sequence data is carried out by using the neural network model, and the FPGA configuration file is compressed and decompressed by using the estimation result, so that the problem that the FPGA configuration process consumes too long time is solved.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to an FPGA configuration file arithmetic compression and decompression method based on a neural network model. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA) has received more and more attention and recognition in the field of neural network hardware acceleration in recent years because of its high performance and high flexibility, especially in the field of real-time requirements. It has a wide range of applications in areas such as high-level automobile automatic driving, stock high-frequency trading, and Internet of Things computing. [0003] Artificial intelligence and deep learning are developing rapidly. In order to cope with increasingly complex neural network models, the integration level of FPGA chips is constantly increasing, and the number of available resources on the chip is constantly increasing. While ...

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a neural network model-based FPGA configuration file arithmetic compression and decompression method to improve the compression rate of the configuration file, thereby effectively solving the problem that the configuration process takes too long question

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