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A quantum chip test structure, its preparation method and test method

A chip testing and quantum technology, applied in the quantum field, can solve the problems of structure sensitivity, abnormal actual function junction, and failure to adopt, and achieve the effect of easy preparation and easy acquisition

Active Publication Date: 2021-06-08
ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this is based on the premise that the process is mature and the formed test junction and functional junction have good consistency. However, the preparation of the quantum chip is different from the traditional semiconductor process, which leads to the fact that the stability of the current process cannot meet the standard, and the test junction may pass. However, the actual functional junction is abnormal
For contact testing, due to the sensitivity of the structure of the superconducting Josephson junction, slight microstructural damage may lead to abnormalities in the superconducting Josephson junction, so the current general understanding is that contact methods cannot be used for measurement

Method used

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  • A quantum chip test structure, its preparation method and test method
  • A quantum chip test structure, its preparation method and test method
  • A quantum chip test structure, its preparation method and test method

Examples

Experimental program
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Effect test

Embodiment 1

[0072] Embodiment 1 of the present invention provides a quantum chip test structure. The implementation details of this embodiment are described in detail below, and the following content is only implementation details provided for easy understanding, and is not necessary for implementing this solution. The schematic diagram of this embodiment can refer to figure 1 ,include:

[0073] a superconducting Josephson junction 20 on the substrate 10; and

[0074] A conductive film layer 30 located on the superconducting Josephson junction, the conductive film layer 30 is used to realize electrical contact with the probe and protect the superconducting Josephson junction.

[0075] In an option of this embodiment, the conductive film layer 30 includes a mixture layer of photoresist and graphite.

[0076] In an option of this embodiment, the conductive film layer 30 includes an organic semiconductor material layer.

[0077] In an option of this embodiment, the conductive film layer ...

Embodiment 2

[0081] Embodiment 2 of the present invention provides a quantum chip test structure, which can be further optimized on the basis of Embodiment 1, wherein the description of the same or similar parts is omitted. The implementation details of this embodiment are described in detail below, and the following content is only implementation details provided for easy understanding, and is not necessary for implementing this solution. The schematic diagram of this embodiment can refer to figure 1 ,include:

[0082] In an option of this embodiment, the conductive film layer 30 includes a mixture layer of photoresist and graphite.

[0083] In another option of this embodiment, the conductive film layer 30 includes an organic semiconductor material layer, for example, it may be P3HT (poly-3 hexylthiophene).

[0084] In another option of this embodiment, the conductive film layer 30 includes a metal layer that is less resistant to chemical corrosion than the metal material covered by th...

Embodiment 3

[0092]Embodiment 3 of the present invention provides a quantum chip test structure, and can be further optimized on the basis of Embodiment 1 or Embodiment 2. This embodiment is similar to the part of Embodiment 1 or Embodiment 2, wherein, the same or similar parts to omit their descriptions. The implementation details of this embodiment that are different from those of Embodiment 1 or Embodiment 2 will be specifically described below. The following content is only implementation details provided for easy understanding, and is not necessary for implementing this solution. The schematic diagram of this embodiment can refer to figure 1 ,include:

[0093] In this embodiment, considering that the area of ​​some three-layer overlapping superconducting Josephson junctions is small, for example, the length and width are about 200nm, and the size (for example, diameter) of the probe is about several microns. Next, if the conductive film layer 30 is disposed on the superconducting Jo...

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Abstract

The invention discloses a quantum chip testing structure, a preparation method and a testing method thereof. The quantum chip test structure includes: a substrate; a superconducting Josephson junction located on the substrate; and a conductive film layer covering the superconducting Josephson junction or its connection structure, and the conductive film layer is used for realizing and probing The pins make electrical contact and protect the superconducting Josephson junction or its connecting structures. In the present invention, the superconducting Josephson junction or its connection structure is covered with a conductive film layer, and the superconducting Josephson junction or its connection structure is not damaged by a probe through the conductive film layer, and the contact test is realized. The structure and method are overall simple, low in cost and high in testing efficiency.

Description

technical field [0001] The invention belongs to the field of quantum technology, and in particular relates to a quantum chip test structure, a preparation method and a test method thereof. Background technique [0002] Quantum computing is a new type of computing model that follows the laws of quantum mechanics to control basic information units for computing. The basic information unit of classical computing is the classical bit, and the basic information unit of quantum computing is the qubit. The classical bit can only be in one state, that is, 0 or 1. Based on the state superposition principle of quantum mechanics, the state of the qubit can be in various states. The superposition state of possibility, so the computational efficiency of quantum computing far exceeds that of classical computing. [0003] Currently, quantum correlation technology is in its infancy. Quantum chips mainly include superconducting quantum chips, semiconductor quantum chips, quantum dot chips,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L39/22H01L39/02H01L39/24G01R31/28G06N10/00
CPCG01R31/2898G01R31/2887G06N10/00H10N60/805H10N60/12H10N60/0912
Inventor 张辉
Owner ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD