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Software testing method for detecting global bit line short-circuit fault of NORFLASH memory

A software testing method and short-circuit fault technology, applied in the field of electronic information, can solve problems such as difficult to detect faults, application software cannot be cured, etc.

Pending Publication Date: 2020-08-21
TIANJIN JINHANG COMP TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] A certain type of comprehensive control machine is equipped with JFM29LV641-E NORFLASH memory chip. Although the FLASH erasing and programming test was carried out after production, the application software could not be cured after delivery. After investigation, it was found that the fault was caused by the The global bit line short-circuit fault caused by the defect, the traditional FLASH test method erases and programs the free FLASH space, and the programming data is mostly regular step 0 and step 1 data, which is used to realize the data line and address line. And the test of FLASH erase programming function, it is difficult to detect this fault

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  • Software testing method for detecting global bit line short-circuit fault of NORFLASH memory
  • Software testing method for detecting global bit line short-circuit fault of NORFLASH memory

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Embodiment Construction

[0012] In order to make the purpose, content, and advantages of the present invention clearer, the specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings and examples.

[0013] figure 1 Is the NOR FLASH test flow chart, such as figure 1 Shown, a kind of test method that uses DSP software to read and write FLASH memory space of the present invention comprises: adopt DSP test software, at first the software in FLASH is cached in the external storage SDRAM, the whole space of FLASH is erased, by specific sequence Program and post-program data verification to identify sector bit line short faults.

[0014] The test process designed by the present invention is divided into three parts, followed by FLASH data backup, FLASH erasing programming test and FLASH data recovery, the test process is as follows figure 1 as shown,

[0015] The test methods are introduced as follows:

[0016] FLASH da...

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Abstract

The invention relates to a software testing method for detecting a global bit line short-circuit fault of a NORFLASH memory. The method comprises, FLASH data backup: after receiving the NORFLASH backup command and the test parameters, the test software backs up specified space data into a cache space and calculates a FLASH read-out data checksum at the same time, calculates a cache space checksumafter backup is completed, compares whether the checksums are consistent or not, if not, sets a command execution state as a check error, and terminates the test; carrying out a FLASH erasing programming test, and erasing FLASH full space; carrying out a programming test on the FLASH designated area according to the programming type; performing read-back verification on the programmed area; circularly executing FLASH erase programming test operation according to different programming types; erasing the whole space of the FLASH; carrying out FLASH data recovery, and resetting the FLASH; programming the data of the cache space to a specified FLASH space; and calculating the checksum of the FLASH and the cache data, and comparing whether the checksums are consistent or not.

Description

technical field [0001] The invention belongs to the technical field of electronic information, and in particular relates to a software testing method for detecting short-circuit faults of global bit lines of a NORFLASH memory. Background technique [0002] A certain type of comprehensive control machine is equipped with JFM29LV641-E NORFLASH memory chip. Although the FLASH erasing and programming test was carried out after production, the application software could not be cured after delivery. After investigation, it was found that the fault was caused by the The global bit line short-circuit fault caused by the defect, the traditional FLASH test method erases and programs the free FLASH space, and the programming data is mostly regular step 0 and step 1 data, which is used to realize the data line and address line. As well as the test of the FLASH erase programming function, it is difficult to detect this fault. This fault needs to be screened out by the chip manufacturer ...

Claims

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Application Information

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IPC IPC(8): G06F11/22G06F11/14G11C29/10
CPCG06F11/2236G06F11/2273G06F11/1448G11C29/10
Inventor 边维张永华李红军
Owner TIANJIN JINHANG COMP TECH RES INST