Inter-processor communication

Abstract

An electronic device (2) comprises a first processor (4) and a second processor (6). An inter-processor communication module (8) is connected to the processors and comprises a high priority mailbox (14) and a low priority mailbox (18). The first processor (4) sends a high or low priority message to the second processor (6). The first processor (4) is arranged such that if it has a high priority message to send to the second processor (6), the first processor (4) places the high priority message in the high priority mailbox (14) and sends an interrupt request to the second processor (6). However, when the first processor (4) has a low priority message to send to the second processor (6), the first processor (4) places the high priority message in the low priority mailbox (18) to be checkedlater without sending an interrupt request to the second processor.

Description

technical field [0001] The invention relates to communication between processors, in particular to communication between two different central processing units corresponding to each other via mailboxes. Background technique [0002] To increase the processing capabilities of modern electronic devices, many such devices are provided with multiple processors or central processing units (CPUs). These could be, for example, separate discrete processors, or could be different processing 'cores' within a single chip. Such processors can work in parallel, for example to accommodate different processing tasks that are completely independent of each other. However, in some cases it is desirable for the processors to communicate with each other. [0003] To facilitate this type of interprocessor communication (IPC), typically a CPU writes data to a location, a 'mailbox', that is shared between itself and another CPU that wishes to communicate with it, and An interrupt request (IRQ)...

AI Technical Summary

Problems solved by technology

[0004] However, applicants have learned that conventional methods are not efficient in terms of power consumption, especially when the interrupted processor is in a low power mode

Normally, the CPU will not ignore the IRQ, and thus the interrupted CPU will wake up from its low power mode and restore its previous hardware state, which takes time and power

Also, once the CPU that is now awake reads the message after being interrupted, said CPU will usually go back to its low power mode, which also takes time and power

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