Vertical semiconductor devices

Abstract

The invention provides a vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality ofwiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.

Description

technical field [0001] Some example embodiments relate to vertical semiconductor devices and / or methods of manufacturing the same. Background technique [0002] Since the device is highly integrated, a vertical NAND (VNAND) flash memory device may have a cell-on-periphery (COP) structure in which vertical memory cells are formed on a peripheral circuit on a substrate. In this case, peripheral circuits may be degraded during formation of vertical memory cells. Therefore, VNAND flash memory devices may suffer from operational failure or characteristic degradation. Contents of the invention [0003] Some example embodiments provide vertical semiconductor devices having excellent electrical characteristics. [0004] Some example embodiments provide methods of fabricating vertical semiconductor devices having improved electrical characteristics. [0005] According to an example embodiment, a vertical semiconductor device may include: a plurality of vertical memory cells on a...

AI Technical Summary

Problems solved by technology

Therefore, VNAND flash memory devices may suffer from operational failure or characteristic degradation

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