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Three-dimensional semiconductor memory device

A storage device and semiconductor technology, applied in the direction of semiconductor devices, static memory, electric solid-state devices, etc., can solve problems such as integration setting restrictions

Pending Publication Date: 2020-09-29
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the cost of the processing equipment used to increase the fineness of patterns would set a practical limit for increasing the integration of two-dimensional or planar semiconductor devices.

Method used

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Embodiment approach

[0044] The upper semiconductor pattern USP may have a tube shape with its bottom closed. The upper semiconductor pattern USP may have a bottom surface in direct physical contact with the lower semiconductor pattern LSP. The upper semiconductor pattern USP may have an interior at least partially filled with the buried insulation pattern VI. Each of the upper semiconductor pattern USP and the buried insulation pattern VI may have a diameter that gradually decreases as the distance from the substrate 100 decreases. In some embodiments, the diameter may decrease monotonically with decreasing distance from the substrate 100 . According to some example embodiments of the inventive concepts, the lower semiconductor pattern LSP and the upper semiconductor pattern USP may serve as channels of a three-dimensional semiconductor memory device.

[0045] For example, the lower semiconductor pattern LSP and the upper semiconductor pattern USP may include silicon (Si), germanium (Ge), or a ...

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Abstract

A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a chargestorage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

Description

technical field [0001] The inventive concept relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device with improved reliability. Background technique [0002] Semiconductor devices have been highly integrated to provide the high performance and lower price that customers expect. Since the integration of semiconductor devices is a factor in determining product prices, the demand for highly integrated semiconductor devices will increase. The integration of a typical two-dimensional or planar semiconductor device is mainly determined by the area occupied by a unit memory cell, so that it is affected by the level of technology for forming fine patterns. However, the processing equipment used to increase the fineness of patterns may set a practical limit to increase the integration of two-dimensional or planar semiconductor devices due to its cost. Accordingly, three-dimensional semiconductor memory devices having three-dimens...

Claims

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Application Information

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IPC IPC(8): H01L27/11563H01L27/11568H01L27/11578
CPCH10B43/00H10B43/20H10B43/30H01L29/7926H01L29/40117H01L29/4234H01L29/42368H10B43/27H10B43/50G11C5/025H10B41/27
Inventor 朴世准李载德张在薰姜振圭洪昇完洪玉千
Owner SAMSUNG ELECTRONICS CO LTD
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