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Fpga-based message deduplication method, device and fpga chip

A message and chip technology, applied in the field of image processing, can solve problems such as increasing the processing pressure of background analysis servers, difficulty in meeting efficient data processing requirements, and increasing the complexity of background processing, so as to improve the efficiency of repeated comparisons and simplify repetitions Comparison process, avoiding the effect of traversal matching

Active Publication Date: 2022-04-15
湖南有马信息技术有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Since the collection and distribution equipment usually completes the function of converging and distributing output of multiple links, and multiple links usually correspond to the Ethernet split points of multiple links, sometimes there are a large number of identical Ethernet data traffic, these repetitive traffic will increase the processing pressure on the background analysis server and increase the complexity of background processing
[0004] In order to solve the problem of link duplicate message filtering, a kind of duplicate message detection method based on CPU platform is provided in the related art, this traditional deduplication method adopts the method of quintuple flow table search, this method deduplication comparison speed Low, and the comparison accuracy is not high, it is difficult to meet the needs of efficient data processing, and in the face of large data traffic, it will generate a large processing burden for the duplicate message detection end

Method used

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  • Fpga-based message deduplication method, device and fpga chip
  • Fpga-based message deduplication method, device and fpga chip
  • Fpga-based message deduplication method, device and fpga chip

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Embodiment Construction

[0045] The core of the application is to provide an FPGA-based message deduplication method, which can realize efficient and fast message deduplication processing; another core of the application is to provide a FPGA-based message deduplication device and a FPGA chips.

[0046] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0047] Network data collection is usually divided into two types, one is the dir...

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Abstract

This application discloses a message de-duplication method based on FPGA. In this method, the look-up table based on the hash value as the reading index address is called to perform repeated matching and comparison of messages based on pipeline operation, which improves the efficiency of de-duplication comparison. ; Since the hash value of traffic data is greatly shortened compared to the data length of traffic data itself, matching and comparison based on hash value can improve the efficiency of matching comparison; and in this method, hash value is used as the read index address, according to Values ​​can be directly read from the historical entries in the lookup table for matching and comparison, avoiding traversal matching of historical traffic data, significantly improving the efficiency of repeated comparisons, and realizing fast packet deduplication. The present application also provides an FPGA-based message deduplication device, equipment and a readable storage medium, which have the above beneficial effects.

Description

technical field [0001] The present application relates to the technical field of image processing, in particular to an FPGA-based message deduplication method, device and an FPGA chip. Background technique [0002] In the field of network analysis and monitoring, the role of network visualization collection and distribution equipment is becoming more and more important. In the network visualization collection, the flow splitter collects the flow data of multiple links, aggregates and splits the output, and introduces the data flow in the link to the back-end analysis server, which plays a role in the visualization platform and user data link. A "Logistics" role for filtering categories. [0003] Since the collection and distribution equipment usually completes the function of converging and distributing output of multiple links, and multiple links usually correspond to the Ethernet split points of multiple links, sometimes there are a large number of identical Ethernet dat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L47/10H04L45/02H04L45/7453G06F15/78H04L47/41
CPCH04L47/29H04L45/02H04L45/7453G06F15/7807H04L47/41
Inventor 吴敏源金玉超
Owner 湖南有马信息技术有限公司
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