Application defined multi-tiered wear-leveling for storage class memory systems

Abstract

A method implemented by a memory device comprises obtaining, by a processor coupled to a memory, a wear-leveling policy from an application executable at the memory device, wherein the wear-leveling policy indicates a memory size by which to perform wear-leveling within an instance, wherein the instance comprises an address range assigned to the application in the memory of the memory device (703); obtaining, by a processor, a request to access the instance (706); and performing, by the processor, wear-leveling on a plurality of memory cells within the instance according to the wear-leveling policy (709).

Description

[0001] Related Applications Cross Application [0002] This application claims priority to U.S. Patent Application No. 15 / 909,582, filed March 1, 2018, with the U.S. Patent Office, entitled "Application-Defined Multi-Layer Wear Leveling for Storage Class Memory Systems," which The entire contents are incorporated herein by reference. Background technique [0003] The wear or physical location of memory cells in a memory system changes depending on how often each cell is programmed. If a memory cell is programmed once, but never actually reprogrammed, the wear associated with that cell will generally be lower. However, if a cell is repeatedly written and erased, the wear associated with that cell will typically be higher. Since physical addresses are used by the host, if the host repeatedly uses the same address to write and overwrite data, the same physical location or cell in the memory system is repeatedly written and erased. Contents of the invention [0004] According...

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However, if a cell is repeatedly written and erased, the wear associated with the cell will typically be higher

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