Memory and its testing method

Abstract

The embodiment of the invention discloses a system-on-chip memory and a testing method thereof. The memory includes: a plurality of physical storage units; a plurality of first logical mapping units, each of the first logical mapping units is electrically connected to at least two of the physical storage units; a second logical mapping unit, the second The logic mapping unit is electrically connected to the first logic mapping unit; the test logic unit is electrically connected to the second logic mapping unit for passing the second logic mapping unit and the first logic The mapping unit tests the physical storage unit; the functional circuit of the system-on-chip is multiplexed as the first logical mapping unit, and the functional circuit is also used to work when not testing the physical storage unit. The test logic composed of the first logic mapping unit, the second logic mapping unit and the test logic unit in the memory of the embodiment of the present invention has advantages such as small area.

Description

technical field [0001] The embodiment of the present invention relates to memory testing technology, in particular to a memory and a testing method thereof. Background technique [0002] With the development of the big data era, the magnitude and complexity of the data that needs to be calculated has also increased dramatically, and the size of high-performance system-on-chip chips has continued to increase. Memory, especially on-chip storage logic, can effectively reduce the number of data transmissions and delays, thereby ensuring the data exchange efficiency of high-performance computing chips. Thus, the demand for on-chip memory is rapidly increasing. [0003] However, the corresponding test logic area of ​​the existing memory is relatively large, which makes the area of ​​the memory large and occupies a relatively large physical area of ​​the system chip, which makes the production and test cost of the chip more and more high. Contents of the invention [0004] The ...

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Problems solved by technology

[0003] However, the corresponding test logic area of ​​the existing memory is relatively large, which makes the area of ​​the memory larger and occupies a higher physical area of ​​the system chip, making the production and testing costs of the chip more and more high.

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