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Novel distributed array and cmos architecture for 2-stack 3D phase-change memory with higher array efficiency

A memory and array technology, applied in the field of three-dimensional electronic memory, can solve problems such as high cost

Active Publication Date: 2021-08-17
YANGTZE ADVANCED MEMORY INDUSTRIAL INNOVATION CENTER CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly
Therefore, the storage density of planar memory cells approaches the upper limit

Method used

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  • Novel distributed array and cmos architecture for 2-stack 3D phase-change memory with higher array efficiency
  • Novel distributed array and cmos architecture for 2-stack 3D phase-change memory with higher array efficiency
  • Novel distributed array and cmos architecture for 2-stack 3D phase-change memory with higher array efficiency

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Embodiment Construction

[0018] The technology is applied in the field of three-dimensional memory. exist figure 1 A general example of a three-dimensional (3D) memory is shown in . in particular, figure 1 is an isometric view of a section of a 3D phase change memory. The memory includes a first layer storage unit 5 and a second layer storage unit 10 . Between the first layer memory cells 5 and the second layer memory cells 10 are a plurality of word lines 15 extending in the horizontal (X) direction. In the depth (Z) direction, a plurality of first bit lines 20 extending along the vertical (Y) direction are above the first layer of memory cells 5, and a plurality of first bit lines 20 extending along the Y direction are below the second layer of memory cells 10. A second bit line 25.

[0019] further as figure 1 As shown in , the sequential structure of bit line, memory cell, word line, memory cell can be repeated along the Z direction to form a stacked configuration. exist figure 1 In an exa...

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Abstract

A three-dimensional memory architecture comprising a bottom cell array of memory cells, a top cell array of memory cells, a plurality of bottom cell bit lines coupled to the bottom cell array, a plurality of top cell bit lines coupled to the top cell array, and coupling multiple wordlines to both arrays. Bitline decoders and wordline decoders are provided to selectively activate bitlines and wordlines. The arrays of memory cells are respectively arranged in offset subsections. Bit lines and word lines are respectively arranged in shifted portions. The bit line decoders are arranged in the offset bit line decoder subsections. The wordline decoders are also arranged in the offset wordline decoder subsection.

Description

technical field [0001] In general, the present disclosure relates to three-dimensional electronic memory, and in particular, the present disclosure relates to increasing the density of memory cells in three-dimensional phase change (3D PCM) memory. Background technique [0002] Planar memory cells are shrunk to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. Therefore, the storage density of planar memory cells approaches the upper limit. There remains a need for three-dimensional (3D) memory architectures that can address the density limitations in planar memory cells. Contents of the invention [0003] The three-dimensional memory and methods disclosed herein solve the problems of the state of the art and provide additional benefits. According to one aspec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L45/00H01L27/02
CPCH01L27/0207H10N70/801H10N70/231H10N70/826H10B63/84
Inventor 刘峻
Owner YANGTZE ADVANCED MEMORY INDUSTRIAL INNOVATION CENTER CO LTD
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