Novel distributed array and contact architecture for 4 stacked 3D PCM memories

Abstract

A three-dimensional memory includes memory cell layers stacked in a depth direction. The bottom cell layer includes a bottom cell array block, the top cell layer includes a top cell array block aligned with the bottom cell array block in a vertical direction, and the at least one intermediate cell layer includes an intermediate cell array block offset from the bottom cell array block in the vertical direction. The memory includes a plurality of bit lines and a plurality of bit line contacts, where a bottom cell bit line contact is connected to the bottom cell bit line, a top cell bit line contact is connected to the top cell bit line and the bottom cell bit line, and an intermediate cell bit line contact is connected to the intermediate cell bit line and located in a space between the bottom cell array blocks.

Description

technical field [0001] In general, the present disclosure relates to three-dimensional electronic memory, and in particular, the present disclosure relates to increasing the density of memory cells in three-dimensional phase change memory (3D PCM). Background technique [0002] Planar memory cells are shrunk to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. Therefore, the storage density of planar memory cells approaches the upper limit. There remains a need for three-dimensional (3D) memory architectures that can address the density limitations in planar memory cells. Contents of the invention [0003] The three-dimensional memory and methods disclosed herein solve the problems of the state of the art and provide additional benefits. According to one aspec...

AI Technical Summary

Problems solved by technology

However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly

Therefore, the storage density of planar memory cells approaches the upper limit

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