Equal-probability DOE limit simulation method for PCIE link design, program and medium

Abstract

The invention discloses an equal-probability DOE limit simulation method for PCIE link design, a program and a medium. The equiprobabilistic DOE limit simulation method for PCIE link design comprisesthe following steps: creating a PCIE simulation link; searching an optimal TXLE factor by utilizing the factor combination; generating a first DOEcase by taking the length factor as a constant and thenon-length factor as a variable; importing the length factor as a variable into any one of the first DOEcase to generate a second DOEcase, wherein the PCIE simulation link is configured with the optimal TXLE factor, and the PCIE simulation link simulates all the second DOEcase; counting the number of the failed second DOEcases corresponding to the same length factor parameter; and judging whetherthe length is the limit length or not according to the number of the failed second DOEcases. The PCIE link design uses an equal probability DOE limit simulation program to realize the method. According to the method, it can be effectively guaranteed that the formed simulation result is equal in probability, and it is significant to count the number of failed second DOEcases corresponding to the same length factor parameter according to the simulation result.

Description

technical field [0001] The invention relates to the field of PCIE link design, in particular to an equal-probability DOE limit simulation method, program and medium for PCIE link design. Background technique [0002] With the rapid development of PCIE, PCIE has now developed to PCIE5.0 and 6.0. PCIE, as the main bus designed for server single boards, is the main signal for interconnecting GPUs, network cards, and SSDs. As the main signal of this platform, PCIE5.0 has a signal rate of 32G. Higher rate means shorter interconnection length and stricter crosstalk and loss requirements. Finding the limit interconnection length to reduce design risk is of great significance to reduce R&D costs. [0003] In the prior art, no matter what kind of optimization algorithm is used for hardware experimental design, it will cause high R&D costs. The cost of PCIE link experimental design to find the limit of PCIE link length is very high; generally, simulation is used to Find the length ...

AI Technical Summary

Problems solved by technology

[0004] The present invention provides an equal-probability DOE limit simulation method for PCIE link design, aiming to solve the problem that when using DOE to determine the PCIE link length limit in the prior art, the probability of DOEcases with different lengths cannot be guaranteed to be equal probability, so the reliability of the results cannot be guaranteed The problem

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