A kind of equal probability doe limit simulation method, program and medium for pcie link design

Abstract

The invention discloses an equal probability DOE limit simulation method, program and medium for PCIE link design. The iso-probability DOE limit simulation method for PCIE link design includes creating a PCIE simulation link; using factor combinations to find the optimal TXLE factor; taking the length factor as a constant and the non-length factor as a variable to generate the first DOEcase; taking the length factor as The variable is imported into any of the first DOEcases to generate the second DOEcase; the PCIE simulation link configures the optimal TXLE factor, and the PCIE simulation link simulates all the second DOEcases; statistics corresponding to the same length factor parameter The number of the second DOEcases that fail; it is judged whether the length is the limit length according to the number of the second DOEcases that fail. PCIE link design implements the method with an isoprobable DOE limit simulation program. The present invention can effectively ensure that the formed simulation results are of equal probability, and the number of the second DOEcases that fail corresponding to the same length factor parameter counted according to the simulation results is meaningful.

Description

technical field [0001] The invention relates to the field of PCIE link design, in particular to an equal probability DOE limit simulation method, program and medium for PCIE link design. Background technique [0002] With the rapid development of PCIE, PCIE has developed to PCIE 5.0 and 6.0. PCIE, as the main bus for server board design, is the main signal for interconnecting GPUs, network cards, and SSDs. PCIE5.0 is the main signal of this platform, and the signal rate has reached 32G. Higher rate means shorter interconnection length, stricter crosstalk and loss requirements. Finding the limit interconnection length to reduce design risk is of great significance to reducing R&D costs. [0003] In the prior art, no matter what kind of optimization algorithm is used for hardware experimental design, it will result in high R&D costs. PCIE link experimental design to find the limit of PCIE link length is very costly; generally, simulation is used to Find the length limit, us...

AI Technical Summary

Problems solved by technology

[0004] The present invention provides an equal-probability DOE limit simulation method for PCIE link design, aiming to solve the problem that when using DOE to determine the PCIE link length limit in the prior art, the probability of DOEcases with different lengths cannot be guaranteed to be equal probability, so the reliability of the results cannot be guaranteed The problem

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