Block floating point computations using reduced bit-width vectors

Abstract

A system for block floating point computation in a neural network receives a block floating point number comprising a mantissa portion. A bit-width of the block floating point number is reduced by decomposing the block floating point number into a plurality of numbers each having a mantissa portion with a bit-width that is smaller than a bit-width of the mantissa portion of the block floating point number. One or more dot product operations are performed separately on each of the plurality of numbers to obtain individual results, which are summed to generate a final dot product value. The final dot product value is used to implement the neural network. The reduced bit width computations allow higher precision mathematical operations to be performed on lower-precision processors with improved accuracy.

Description

Background technique

[0001] Block floating-point number format allows dynamic range and precision to be scaled independently. By reducing the precision, the system performance of a processor (such as a hardware accelerator) can be increased. However, reduced precision may affect system accuracy. For example, the block floating-point number format can be used for neural networks that can be implemented in many application areas for tasks such as computer vision, robotics, speech recognition, medical image processing, computer games, augmented reality, virtual reality, etc. . While reduced precision can improve the performance of different functions of neural networks (including the speed at which classification and regression tasks are performed for object recognition, lip reading, speech recognition, detecting unusual transactions, text prediction, and many others), However, accuracy may be adversely affected. Contents of the invention

[0002] This Summary is provided t...

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