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Ddr5 client pmic power up sequence and state transitions

A state and power state technology, applied in the field of realizing DDR5 client PMIC power-on sequence and state transition, which can solve problems such as not allowing

Pending Publication Date: 2020-12-29
RENESAS ELECTRONICS AMERICA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Conventional PMICs for DDR5 client PMICs and SODIMM / UDIMMs do not allow seamless transitions from specific power states (i.e., P1 state and P3a state) without requiring additional pins

Method used

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  • Ddr5 client pmic power up sequence and state transitions
  • Ddr5 client pmic power up sequence and state transitions
  • Ddr5 client pmic power up sequence and state transitions

Examples

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Embodiment Construction

[0028] Embodiments of the present invention include providing a DDR5 client PMIC power-up sequence and state transition that can (i) seamlessly transition from a low-power P1 state to an idle P3a state, (ii) use existing pins for PMIC circuitry, ( iii) Use VR_EN pin and registers to control entering or exiting from low power state, (iv) support safe operation mode and programmable operation mode, (v) support bidirectional PWR_GOOD pin or output only PWR-GOOD pin, (vi) Support VR Disable command via VR_EN pin or VR Disable command on I2C / I3C bus, (vii) implemented as part of DDR5 unbuffered memory block, (viii) implemented as buffered memory block, (ix ) is implemented as part of a registered double data rate fifth generation memory module, and / or (x) is implemented as one or more integrated circuits.

[0029] Embodiments of the present invention may be configured to be implemented in double data rate fifth generation (DDR5) random access memory (RAM) modules. Low power hardwa...

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Abstract

An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry toa low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

Description

[0001] This application is related to U.S. Provisional Application No. 62 / 868,019, filed June 28, 2019, which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates generally to computer memory, and more particularly to a method and / or apparatus for implementing a DDR5 client PMIC power-on sequence and state transition. Background technique [0003] Consumers are looking to reduce the power consumption of computing devices. As computing devices become more portable, power consumption becomes increasingly important to ensure long battery life. In particular, portable computing devices such as laptops, notebooks, and netbooks have stringent current requirements under certain conditions. Every component of a computing device needs to be optimized to reduce power consumption. [0004] DDR5 SODIMM / UDIMM implements various power states to minimize power consumption. Power states (or P-states) are voltage-frequency pairs that ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/3296
CPCG06F1/3296G06F1/3206G06F1/3275
Inventor S·A·帕特尔任晨晓
Owner RENESAS ELECTRONICS AMERICA
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