Gate drive circuit and display panel

Abstract

The application provides a gate drive circuit and a display panel, including an M-level clock signal line, an N-level gate signal line, and a plurality of first pull-down modules. The period of the clock signal is (a*T), and the duty cycle is ( T-2) / (2*T), the delay time of two adjacent clock signals is a, the nth m , (n m +j*M) level gate signal line is respectively nth m One corresponding cycle of the stage clock signal line is synchronous, and the falling edge and rising edge of the signal at the first input end of the first pull-down module respectively pull down the signal at the first output end and the signal at the second output end of the first pull-down module, if k%M is an odd number , then the gate signal line of the kth stage is connected to the first output end, and the corresponding first input end is connected to the clock signal line of the (k%M)th stage; otherwise, the gate signal line of the kth stage is connected to the second output end, corresponding to The first input terminal of is connected to the clock signal line of the [(k%M)+f+g1*T] stage, M is an even number greater than 2, N≥M, 1≤n m ≤M, T=M, j>0, f=(T‑2) / 2, [(k%M)+f+g1*T] is an odd number; this solution can improve the charging time of pixels to improve the display panel Displays the uniformity of the picture.

Description

Technical field [0001] The present application relates to the field of display, and in particular to the field of display panel manufacturing techniques, and specific to gate drive circuits and display panels. Background technique [0002] For LCD (Lip1uid Crystal Disp1lay, LCD) panel, the gate driving circuit is shifted to the same side of the source driving circuit, and the drop circuit can be set in the pair of the source driving circuit, which can be narrow The border is also ensured that the pixels have sufficient charging time. [0003] At present, the pull-down circuitry is made by transforming the clock signal to obtain a desired drop signal, and then the pull-down signal acts on the corresponding gate signal to achieve a drop down of the gate signal; however, the existing drop-down circuit can only be applied. The clock signal of a duty cycle is 50%, and for a clock signal having a duty ratio of less than 50%, the rising edge of the partial clock signal is delayed by a d...

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present application provides a gate drive circuit and a display panel, wherein the falling edge and rising edge of the signal at the first input end of the first pull-down module respectively pull down the signal at the first output end and the signal at the second output end of the first pull-down module. A clock signal whose ratio is (T-2) / (2*T) passes through "if k%M is an odd number, then the gate signal line of the kth stage is connected to the first output end, and the corresponding first input end is connected to the (kth %M) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end, and the corresponding first input end is connected to the [(k%M)+f+g1*T] level clock signal line, And [(k%M)+f+g1*T] is an odd number", wherein M is the total odd number of the clock signal line, T=M, f=(T-2) / 2; to solve the existing LCD Part of the gate signal in the pixel drive circuit of the panel cannot be pulled down in time, which reduces the charging time of the corresponding pixel, so that the brightness of the pixels in different areas of the LCD panel varies greatly.

Images