Gate drive circuit and display panel

Abstract

The invention provides a gate drive circuit and a display panel. The gate drive circuit comprises M stages of clock signal lines, N stages of gate signal lines and a plurality of first pull-down modules, wherein the period of each clock signal is (a*T), the duty ratio of each clock signal is (T-2) / (2*T), the delay time of two adjacent stages of clock signals is a, and the nm-th and (nm + j * M)thstages of gate signal lines are respectively synchronized by one corresponding period; the falling edge and the rising edge of the signal of the first input end of the first pull-down module pull downthe signal of the first output end and the signal of the second output end of the first pull-down module respectively, if k% M is an odd number, the kth-stage of gate signal line is connected with the first output end, and the corresponding first input end is connected with the (k% M) th-stage clock signal line; whereas the kth-stage of gate signal line is connected with the second output end, the corresponding first input end is connected with the [(k% M) + f + g1 * T] th-stage clock signal line, M is an even number greater than 2, N is greater than or equal to M, 1 < = nm < = M, T = M, j >0, f = (T2) / 2, and [(k% M) + f + g1 * T] is an odd number. According to the scheme, the charging time of the pixels can be improved so as to improve the uniformity of a display image of the display panel.

Description

technical field [0001] The present application relates to the field of display technology, in particular to the field of display panel manufacturing technology, in particular to a gate drive circuit and a display panel. Background technique [0002] For LCD (Lip1uid Crystal Display, liquid crystal display) panels, using narrow frame technology to move the gate drive circuit to the same side of the source drive circuit, and setting the pull-down circuit on the opposite side of the source drive circuit, can achieve narrow The frame also ensures that the pixels have sufficient charging time. [0003] At present, the pull-down circuit obtains the required pull-down signal by transforming the clock signal, and then applies the pull-down signal to the corresponding gate signal to realize the pull-down of the gate signal; however, the existing pull-down circuit can only be applied For a clock signal with a duty cycle of 50%, for a clock signal with a duty cycle lower than 50%, the...

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present application provides a gate drive circuit and a display panel, wherein the falling edge and rising edge of the signal at the first input end of the first pull-down module respectively pull down the signal at the first output end and the signal at the second output end of the first pull-down module. A clock signal whose ratio is (T-2) / (2*T) passes through "if k%M is an odd number, then the gate signal line of the kth stage is connected to the first output end, and the corresponding first input end is connected to the (kth %M) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end, and the corresponding first input end is connected to the [(k%M)+f+g1*T] level clock signal line, And [(k%M)+f+g1*T] is an odd number", wherein M is the total odd number of the clock signal line, T=M, f=(T-2) / 2; to solve the existing LCD Part of the gate signal in the pixel drive circuit of the panel cannot be pulled down in time, which reduces the charging time of the corresponding pixel, so that the brightness of the pixels in different areas of the LCD panel varies greatly.

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