Computing device and method for loading or updating data

Abstract

The embodiment of the invention relates to a computing device and a method for updating data, and relates to the field of computers. According to the invention, the method comprises the steps that a first processing unit sends a write instruction to a first memory via a network-on-chip, the write instruction comprising a first address and a plurality of items of write data; the first processing unit sends an emptying instruction; the first processing unit sends an updating instruction to the near memory processing unit through the network-on-chip, wherein the updating instruction comprises a first address and a plurality of second addresses; in response to the update instruction, the near memory processing unit performs a predetermined operation on a plurality of data items on a pluralityof second addresses of the first memory and a plurality of write-in data on the first address to generate a plurality of updated data items; and the near memory processing unit stores the updated plurality of data items to a plurality of second addresses. Therefore, the data can be flexibly processed in the near-memory processing unit, and the data movement overhead in the data updating process can be reduced.

Description

technical field [0001] Embodiments of the present disclosure generally relate to the field of computers, and in particular to computing devices, methods for loading data, and methods for updating data. Background technique [0002] Embedded table data reading has been widely used in many computer applications, especially in artificial intelligence applications such as personalized recommendation models. For the deep learning recommendation model (DLRM), the sparse embedding operation represented by SparseLengthsSum (SLS) consists of the following two actions: first, a small amount of sparse lookup is performed in the huge embedding table, and then the embedding table items are reduced, For example pooling. [0003] Traditional schemes implement sparse embedding operations through Near Memory Processing (NMP). refer to figure 1 , which shows a schematic block diagram of an architecture 100 for near-memory data processing according to the prior art. Such as figure 1 As sh...

AI Technical Summary

Problems solved by technology

[0004] However, how to efficiently transfer the read data from the main memory 140 to the vector processing unit 110 through the network-on-chip is a challenge

Furthermore, it is still expensive to read entries into the vector processing unit 110 so that weight gradients can be added to these entries, and it is still challenging to transmit write data through the on-chip network.

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