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FPGA-based Ethernet port flow rate limiting system and method

A technology of Ethernet and flow limitation, which is applied in the field of FPGA-based Ethernet port flow rate limiting system, which can solve the problems that it is difficult to meet the requirements of controllable substation switches, and the Ethernet switch chip does not support the port rate limit function, etc., to meet the requirements Effect

Inactive Publication Date: 2021-02-19
深圳市源拓光电技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Existing Ethernet switching chips do not support the port speed limit function, and it is difficult to meet the requirements of controllable substation switches

Method used

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  • FPGA-based Ethernet port flow rate limiting system and method
  • FPGA-based Ethernet port flow rate limiting system and method
  • FPGA-based Ethernet port flow rate limiting system and method

Examples

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Embodiment Construction

[0020] The present invention will be further described below in conjunction with the description of the drawings and specific embodiments.

[0021] Such as Figure 1 to Figure 3 As shown, an FPGA-based Ethernet port flow rate limiting system includes a CPU (Central Processing Unit) unit 101, a first PHY (port physical layer) unit 102, an FPGA (Field Programmable Logic Gate Array) unit 103, a first Two PHY units 104 and a network interface 105, the network interface 105 is bidirectionally connected to the input and output of the second PHY unit 104, the second PHY unit 104 is bidirectionally connected to the input and output of the FPGA unit 103, and the FPGA unit 103 Two-way connection with the input and output of the first PHY unit 102, the two-way connection between the first PHY unit 102 and the SGMII interface input and output of the CPU unit 101, the output of the CPU unit 101 is connected to the FPGA unit through the IIC bus Connect with 103.

[0022] The CPU unit 101 ...

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Abstract

The invention provides an FPGA-based Ethernet port flow rate limiting system, which comprises a CPU unit, a first PHY unit, an FPGA unit, a second PHY unit and a network interface, and is characterized in that the network interface is in bidirectional connection with the input and output of the second PHY unit, the second PHY unit is in bidirectional connection with the input and output of the FPGA unit, and the second PHY unit is in bidirectional connection with the FPGA unit. The FPGA unit is in bidirectional connection with the input and output of the first PHY unit, the first PHY unit is in bidirectional connection with the input and output of an SGMII interface of the CPU unit, and the output end of the CPU unit is connected with the FPGA unit through an IIC bus. The invention furtherprovides an FPGA-based Ethernet port flow rate limiting method. The invention has the beneficial effects that Ethernet port flow limitation can be realized, and the requirements of an intelligent substation can be met.

Description

technical field [0001] The invention relates to an Ethernet port flow rate limiting system, in particular to an FPGA-based Ethernet port flow rate limiting system and method. Background technique [0002] Existing Ethernet switch chips do not support the port speed limit function, and it is difficult to meet the requirements of controllable substation switches. Contents of the invention [0003] In order to solve the problems in the prior art, the present invention provides an FPGA-based Ethernet port traffic rate limiting system and method. [0004] The present invention provides a FPGA-based Ethernet port flow rate limiting system, comprising a CPU unit, a first PHY unit, an FPGA unit, a second PHY unit and a network interface, and the network interface is connected to the input and output of the second PHY unit bidirectional connection, the second PHY unit is bidirectionally connected to the input and output of the FPGA unit, the FPGA unit is bidirectionally connected ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/801H04L12/823H04L47/32
CPCH04L47/10H04L47/32H04L47/29
Inventor 鞠小育陈守卫胡川
Owner 深圳市源拓光电技术有限公司