Multi-deck memory device including buffer circuitry under array
A circuit system and buffer technology, which is applied in the direction of read-only memory, static memory, digital memory information, etc.
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[0014] The techniques described herein include memory devices having multiple layers of memory cells. The memory devices include separate page buffer circuitry for respective ones of the memory device layers. The page buffer circuitry of the memory device may be located below the memory array of the memory device. The memory cells of a memory device are organized in blocks. Each block contains parts from different layers. A memory device includes different driver circuits for different blocks. A memory device includes different data lines (eg, bit lines) for different layers. The data lines of one layer are electrically separated from the data lines of the other layer. A memory device includes different sets of access lines (eg, word lines) for different blocks. Portions of the same block may share the same set of access lines. Reference below Figure 1 to Figure 7 Other structures, operations, and improvements and advantages of the memory device are described in detail...
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