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Multi-deck memory device including buffer circuitry under array

A circuit system and buffer technology, which is applied in the direction of read-only memory, static memory, digital memory information, etc.

Pending Publication Date: 2021-02-26
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as described in more detail below, incorporating such improvements into some conventional memory devices (e.g., single-layer memory devices) can pose challenges

Method used

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  • Multi-deck memory device including buffer circuitry under array
  • Multi-deck memory device including buffer circuitry under array
  • Multi-deck memory device including buffer circuitry under array

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0014] The techniques described herein include memory devices having multiple layers of memory cells. The memory devices include separate page buffer circuitry for respective ones of the memory device layers. The page buffer circuitry of the memory device may be located below the memory array of the memory device. The memory cells of a memory device are organized in blocks. Each block contains parts from different layers. A memory device includes different driver circuits for different blocks. A memory device includes different data lines (eg, bit lines) for different layers. The data lines of one layer are electrically separated from the data lines of the other layer. A memory device includes different sets of access lines (eg, word lines) for different blocks. Portions of the same block may share the same set of access lines. Reference below Figure 1 to Figure 7 Other structures, operations, and improvements and advantages of the memory device are described in detail...

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PUM

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Abstract

Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a substrate, a first deck including first memory cell strings located over the substrate, a second deck including second memory cell strings and located over the first deck, first data lines located between the first and second decks and coupled to the first memory cell strings, second data lines located over the second deck and coupled to the second memory cell strings, and first and second circuitries. The first and second data lines extending in a direction from a first portion of thesubstrate to a second portion of the substrate. The first buffer circuitry is located in the first portion of the substrate under the first memory cell strings of the first deck and coupled to the first data lines. The second buffer circuitry is located in the second portion of the substrate under the first memory cell strings of the first deck and coupled to the second data lines.

Description

technical field [0001] Embodiments described herein generally include memory devices, and more specifically, relate to memory devices having multiple layers of memory cells. Background technique [0002] Memory devices are widely used in computers and many electronic items to store information. A memory device has a plurality of memory cells. The memory device performs a write operation to store information in the memory cells, a read operation to read the stored information, and an erase operation to erase information (e.g., outdated Information). Memory cells in a memory device are typically organized in blocks. A memory device has access lines for accessing blocks during memory operations (e.g., read, write, or erase operations), and for carrying information to be stored in or read from the blocks (e.g., A data line in the form of a signal). The memory device also has driver circuitry for providing signals to the circuit elements of the block, and buffer circuitry fo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11524H01L27/11529H01L27/11556H01L27/1157H01L27/11573H01L27/11582G11C16/04H10B41/35H10B41/27H10B41/41H10B43/27H10B43/35H10B43/40
CPCG11C16/0483H10B41/41H10B41/35H10B43/40H10B41/27H10B43/35H10B43/27G06F13/1673G11C5/025G11C5/063G11C7/1015G11C2207/2209G11C7/1075G11C16/10G11C16/26G11C11/5642G11C11/5628G11C11/4096G11C16/16G11C11/4094
Inventor 田中智晴
Owner MICRON TECH INC