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Fail-safe counter evaluator to insure proper counting by counter

A fail-safe, counter technology, applied in instruments, pulse technology, measuring devices, etc., can solve problems such as counting failures

Pending Publication Date: 2021-03-02
SIEMENS AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Extraneous pulses will also constitute a count failure

Method used

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  • Fail-safe counter evaluator to insure proper counting by counter
  • Fail-safe counter evaluator to insure proper counting by counter
  • Fail-safe counter evaluator to insure proper counting by counter

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Embodiment Construction

[0016] In order to facilitate understanding of the embodiments, principles and features of the present invention, they will be explained hereinafter with reference to implementations in the exemplary embodiments. In particular, they are described in the context of a fail-safe counter evaluator configured to test fail-safe counters to ensure correct counting operation (no missed counts) therein. However, embodiments of the invention are not limited to use in the described apparatus or methods.

[0017] The components and materials described below as making up the various embodiments are intended to be illustrative and not restrictive. Many suitable components and materials which perform the same or a similar function as the materials described herein are intended to be within the scope of embodiments of the invention.

[0018] By using two counters (a and b), where the first counter (a) is driven by the input to be counted, while sending test pulses to the second counter (b) f...

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Abstract

A fail-safe counter evaluator (200) is provided to insure proper counting operations by fail-safe counters. The fail-safe counter evaluator comprises a first microprocessor (205-1), a first counter (212-1), a second counter (212-2), a second microprocessor (205-2) and a test channel (210-2, 210-4). The first counter (212-1) is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses (210-1). The second counter (212-2) is disposed in the first microprocessor and configured to undergo a test (210-2: test channel). The test channel(210-2) is configured to send an input test signal to the second counter based on test pulses (215-4: active test pulses) from the second microprocessor. The first microprocessor and the second microprocessor are synchronized (217) so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

Description

technical field [0001] Aspects of the invention generally relate to a fail-safe counter evaluator for evaluating a counter to ensure correct counting operation of the counter. Background technique [0002] Counters can be used to count up or count down. Counter circuits are usually constructed from multiple flip-flops connected in cascade or software code. Counters are very widely used components in digital circuits and are manufactured as separate integrated circuits and also incorporated as part of larger integrated circuits. [0003] The term "fail-safe" in engineering refers to a design feature or practice that, in the event of a specific type of failure, causes no or minimal harm to other equipment, the environment, or people way inherently responds. A system that is "fail-safe" does not mean that failure is impossible or unlikely, but rather that the design of the system prevents or mitigates the unsafe consequences of system failure. Fail-safe means that the equip...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K21/40G01R31/3185
CPCG01R31/318527H03K21/40H03K21/406
Inventor 史蒂芬·佩里·帕菲特史蒂芬·M·豪斯曼
Owner SIEMENS AG
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