DRAM fault correlation analysis method based on sequence mode

Abstract

The invention discloses a DRAM (Dynamic Random Access Memory) fault correlation analysis method based on a sequence mode, which comprises the following steps: filtering non-DRAM faults in a fault database to obtain required DRAM fault data; obtaining a DRAM fault sequence database; establishing a sequence DRAM fault sequence database; setting a support degree by adopting a GSP algorithm, scanningthe sequence DRAM fault sequence database, and obtaining the support degrees of all DRAM fault sequences meeting the support degree requirements; screening out sequence rules of DRAM serious faults, DRAM serious faults, DRAM non-serious faults and DRAM serious faults, and calculating confidence coefficients of the sequence rules; screening out sequence rules with confidence greater than 60%; if asequence rule reflecting the DRAM severe fault and the DRAM severe fault occurs, indicating that the DRAM severe fault and the DRAM severe fault have relevance; If the sequence rule reflecting the association between the DRAM non-severe fault and the DRAM severe fault does not occur, indicating that the DRAM non-severe fault does not cause the DRAM severe fault. According to the method, the prediction and early warning problems concerned by fault analysis and prediction are solved, the method has high credibility and universality, and the analysis execution efficiency is optimized.

Description

technical field [0001] The invention relates to a DRAM fault correlation analysis method based on a sequence pattern, which belongs to the technical field of computers. Background technique [0002] In supercomputers, it is often considered that there is a causal relationship between DRAM (memory) single faults and DRAM multiple faults, that is, multiple occurrences of DRAM single faults on a certain CPU node will lead to the occurrence of multiple DRAM faults on this CPU node. In the Sunway series of supercomputers, an early warning mechanism for DRAM single faults and DRAM multiple faults is designed. This mechanism increases the complexity of the CPU design and brings overhead in terms of chip area, power consumption, and fault tolerance. In addition, the impact of DRAM multiple errors on subsequent DRAM multiple errors also needs to be analyzed. Therefore, how to obtain the connection between DRAM single fault and DRAM multiple faults, DRAM multiple faults and DRAM mul...

AI Technical Summary

Problems solved by technology

This mechanism increases the complexity of CPU design and brings overhead in terms of chip area, power consumption, and fault tolerance.

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