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Semiconductor memory device and method of manufacturing semiconductor memory device

A storage device and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as difficult film thickness

Pending Publication Date: 2021-03-19
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, in this method, it is difficult to increase the thickness of the film, and there is a possibility that the insulating layer may be replaced by a conductive layer.

Method used

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  • Semiconductor memory device and method of manufacturing semiconductor memory device
  • Semiconductor memory device and method of manufacturing semiconductor memory device
  • Semiconductor memory device and method of manufacturing semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0040] Next, preferred embodiments will be described in detail with reference to the drawings.

[0041] figure 1 It is a schematic configuration cross-sectional view showing a configuration example of the semiconductor memory device according to the embodiment, when viewed from above.

[0042] The semiconductor storage device 10 includes two first slits ST1, a storage portion MEM sandwiched by the two first slits ST1, an oxidation bus region OXB sandwiched by the two second slits ST2, and a gate isolation portion SHE. .

[0043] Here, the oxidation bus region OXB is disposed so as to penetrate in the vertical direction, and can be used as a region through which contacts for electrical connection pass.

[0044] The first slit ST1 is used to introduce hot phosphoric acid or the like when removing the sacrificial layer SN described later by hot phosphoric acid or the like when manufacturing the semiconductor memory device 10 .

[0045] Memory cells MC are three-dimensionally a...

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PUM

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Abstract

An embodiment provides a semiconductor memory device and a method of manufacturing the semiconductor memory device, which can more easily hinder replacement of an insulating layer and a conductive layer in a region where a contact is provided so as to penetrate through a stacked body in an up-and-down direction. According to one embodiment, a semiconductor memory device includes: a substrate; anda stacked body laminated above the substrate, the stacked body having a first laminated portion in which first insulating layers and second insulating layers are alternately laminated, and a second laminated portion in which conductive layers and first insulating layers are alternately laminated. The semiconductor memory device includes a pillar extending in a stacking direction of the second laminated portion in the second laminated portion and having a memory cell formed at an intersection with at least a portion of the plurality of conductive layers. The second insulating layer includes aninner side portion including a first insulating material, and an end face side portion including a second insulating material.

Description

[0001] related application [0002] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2019-170525 (filing date: September 19, 2019). This application incorporates the entire content of the basic application by referring to this basic application. technical field [0003] Embodiments of the present invention relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device. Background technique [0004] In a manufacturing process of a three-dimensional nonvolatile memory such as a three-dimensional NAND memory, for example, a laminate of conductive layers is formed by replacing a plurality of insulating layers with conductive layers. [0005] In addition, since the electrically connected contacts are arranged so as to penetrate the laminated body in the vertical direction, the insulating layer may be maintained as it is without replacing a part of the laminated body with the conductive l...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11524H01L27/11556H01L27/1157H01L27/11582
CPCH10B41/35H10B41/27H10B43/35H10B43/27H10B43/10H10B43/50H10B43/40H01L21/76877H01L23/53295H01L21/76802H01L23/5226H01L21/31111H10B69/00
Inventor 野田耕生
Owner KIOXIA CORP